FPGA启动器
FPGA Starter (2024-02-22, Verilog, 0KB, 下载0次)
FPGA收发器，，
FPGA transceiver,, (2023-10-03, Verilog, 0KB, 下载1次)
用于Pano G2设备的基于网络的加载器和闪光器
Network based loader and flasher for Pano G2 devices (2022-09-26, Verilog, 9558KB, 下载0次)
Open Bench逻辑嗅探器（Devon Core，Verilog）（3.08，带边缘触发器）
Open Bench Logic Sniffer (Demon Core, Verilog) (3.08 with edge triggers) (2017-10-19, Verilog, 90KB, 下载0次)
verilog-mips处理器，，
verilog-mips-processor,, (2012-03-02, Verilog, 14KB, 下载0次)
SystemVerilog中的MNIST分类器，，
MNIST-classifier-in-SystemVerilog,, (2017-07-26, Verilog, 147896KB, 下载0次)
Verilog通用异步收发器
Verilog UART (2013-06-04, Verilog, 3KB, 下载0次)
实现8-3编码器 用简单的Verilog语言实现8-3编码器，可拓展为各种类型编码器
8-3 encoder A simple Verilog language is used to implement 8-3 encoders, which can be expanded to various types of encoders (2020-12-20, Verilog, 56KB, 下载0次)
Verilog Micron公司技术支持发给我的SDRAM控制器代码
SDRAM controller code from Verilog micron technical support (2020-06-29, Verilog, 291KB, 下载1次)
通过vivado实现38译码器，通过不同的输入实现相应的输出，低电平有效
The 38 decoder is realized by vivado, and the corresponding output is realized by different input. The low level is effective (2020-03-10, Verilog, 118KB, 下载6次)
SPI串行接口控制器，内含一个verilog代码和一个接口说明文档
SPI serial interface controller (2019-05-24, Verilog, 15KB, 下载5次)
：设计一个1MHz的FIR低通滤波器。
① 时钟信号频率16MHz;
② 输入信号位宽8bits，符号速率16MHz；
A 1MHz FIR low pass filter is designed.
(1) The clock signal frequency is 16MHz;
(2) The input signal has a bit width of 8 bits and a symbol rate of 16 MHz; (2019-05-19, Verilog, 51KB, 下载0次)
CAN驱动器-MCP2515-接口程序-Verilog
CAN Driver-MCP2515-Interface Program-Verilog (2018-12-09, Verilog, 16KB, 下载11次)
999计数器，S8置S1递减有复位功能，FPGA验证
999 counter, S8 has S1 reset function, FPGA verification. (2018-05-11, Verilog, 10695KB, 下载0次)
fir滤波器的简单实现，主要用于学习与理解
Simple implementation of the fir filter, mainly for learning and understanding (2018-02-03, Verilog, 1KB, 下载8次)
产生相差90°的AB相脉冲，并且模拟AB相位的超前或滞后，用于ABZ编码器信号的分析
The AB phase pulse with a difference of 90 degrees is produced and the AB phase is simulated forward or lagging, for the analysis of the signal of the ABZ encoder (2018-01-03, Verilog, 5129KB, 下载13次)
fir滤波器源代码及测试程序,有限脉冲滤波器的源程序及测试程序 ,已经通过仿真了
Filter source code and test procedures,Finite pulse filter source and test procedures, has been through the simulation (2017-12-27, Verilog, 137KB, 下载5次)
SDRAM控制器 带仿真模型文件 仿真通过
Simulation model file simulation through SDRAM controller (2017-12-07, Verilog, 2762KB, 下载9次)
简化的16位的cpu的设计，有缓冲器，指令存储器，数据存储器等基本模块组成
The simplified 16 bit CPU design consists of a buffer, instruction memory, data memory and other basic modules (2017-12-01, Verilog, 17833KB, 下载2次)
这是用verilog 实现的同步计数器。
this is a code for synchronous counter written in verilog. (2017-08-12, Verilog, 6KB, 下载4次)