流水线RISC V处理器的实现，具有许多有用的功能，如完全旁路、动态分支预测、单周期和多周期指令、ALU单元与乘法单元并行工作，以及重新排序缓冲区以保证顺序终止。
Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and multi cycle instructions, ALU unit works in parallel with a multiplication unit, and Reorder Buffer to guarantee in-order termination. (2024-02-11, Verilog, 0KB, 下载0次)
设计一个哈夫曼编码器
要求对一段数据序列进行哈夫曼编码，使得平均码长最短，输出各元素编码和编码后的数据序列。
① 组成序列的元素是[0-9]这10个数字，每个数字其对应的4位二进制数表示。比如5对应0101，9对应1001。
② 输入数据序列的长度为256。
③ 先输出每个元素的编码，然后输出数据序列对应的哈夫曼编码序列。
Designing a Huffman Encoder
Huffman coding is required for a data sequence to minimize the average code length and output the coded and coded data sequence of each element.
(1) The elements that make up the sequence are the 10 digits [0-9], and each digit is represented by its corresponding 4-bit binary number. For example, 5 corresponds to 0101, 9 corresponds to 1001.
(2) The length of the input data sequence is 256.
(3) First output the encoding of each element, and then output the Huffman encoding sequence corresponding to the data sequence. (2019-06-19, Verilog, 256KB, 下载1次)
11位巴克码序列峰值检测器，巴克码序列为11`b 11100010010。
① 能够检测巴克码序列峰值；
② 在存在1bits错误情况下，能够检测巴克码序列峰值。
③ 写出测试仿真程序
11-bit Barker code sequence peak detector, Barker code sequence is 11 `b 11100010010. Requirement
(1) The peak value of Barker code sequence can be detected;
(2) In the case of 1 bits error, the peak value of Barker code sequence can be detected.
(3) Write the test simulation program. (2019-06-19, Verilog, 215KB, 下载1次)
数字频率计
数字频率计的原理十分简单，简单的就是一句话和一幅图而已。
一句话：测量被测信号的频率，要清楚频率的定义，一言以蔽之，就是1s中信号的周期数，这不就是周期的倒数吗？
根据频率的定义，我们测量被测信号1s中变化的次数即可，即1s中的周期数。
首先我们设置一个基准时钟信号，频率为1Hz，从第一个上升沿开始计数（被测信号的上升沿数），直到下一个上升沿到达时停止计数，对数据进行锁存，再到达下一个上升沿时，对计数器进行清零，准备下一次的测量。
Digital Frequency Meter (2019-04-25, Verilog, 1KB, 下载0次)
该代码实现了一个基于Wishbone总线协议的DMA控制器，由于SOC可集成的模块越来越多，本文设计的DMAC包含了31个可编程的DMA通道，能够处理多个DMA传输请求。由于数据在Wishbone总线上传输，在总线接口方面，本文设计的DMAC提供了两个既可以作为主机接口又可以作为从机接口的Wishbone接口。当有多个外设同时发出DMA请求时，本文设计的DMAC采用循环优先级和动态优先级相结合的方式，实现了通道仲裁器二级仲裁的功能。为了提高传输效率，本文设计的DMAC不仅支持数据块的传输，还支持高效的分散/集中DMA传输方式。
In this thesis, after in-depth understanding of Wishbone bus protocol and DMA technology, present a design concept of a DMAC integrated into a Wishbone bus based SOC. The DMAC designed in this thesis contains thirty-one programmable DMA channels, which can handle multiple DMA transfer request. As the data is transmitted over the Wishbone bus, the DMAC provides two Wishbone interfaces that can act as a host interface or as a slave interface. When several peripherals issue DMA transfer request at the same time, the DMAC adopts the combination of cyclic priority and dynamic priority to realize the secondary arbitration function of channel arbiter. In order to improve the transmission efficiency, the DMAC not only supports the transmission of data blocks, but also supports efficient scatter/gather DMA transfer mode. (2018-05-28, Verilog, 73KB, 下载7次)
状态机由状态寄存器和组合逻辑电路构成，能够根据控制信号按照预先设定的状态进行状态转移，是协调相关信号动作、完成特定操作的控制中心.
The state machine is composed of state register and combinational logic circuit. It can transfer state according to the state of control according to the predefined state. It is the control center that coordinates the action of related signal and completes the specific operation. (2018-05-04, Verilog, 5805KB, 下载0次)
spi通讯协议，采用第三种CPOL=1，CPHA=1，（1）通过边沿检测技术得出SCK上升沿与下降沿标志,用于下面状态机中的数据采样及发送。
（2）根据时序图，采用1个状态机分别在SCK上升沿实现数据采样（该固件未调用下降沿数据发送）。无论是采样还是发送，都是高位在前，从Bit[7]到Bit[0]，共8位数据。将采集到的八位数据存放入一个16位寄存器中。
SPI communication protocol, using third kinds of CPOL=1, CPHA=1, (1) through edge detection technology to get SCK rising edge and falling edge mark, for the next state machine in the data sampling and sending.
(2) according to the sequence diagram, 1 state machines are used to implement the data sampling on the rising edge of SCK (the firmware does not call the data sent along the falling edge). Whether it is sampling or sending, are all high before, from Bit[7] to Bit[0], a total of 8 bits of data. The collected eight bit data is stored in a 16 bit register. (2017-10-16, Verilog, 3044KB, 下载2次)
倒车雷达实例，每100ms产生1个超声波
需的10us高脉冲激励，并用数码管以16
示经过滤波处理的回响信号的高脉冲计
10us为单位），与此同时，蜂鸣器根据
近，也会相应的发出不同频率的响声。
Reversing radar example produces 1 ultrasonic waves per 100ms
The 10us requires high pulse excitation and uses a digital tube to 16
A high pulse meter for filtering an echo signal
10us as a unit, at the same time, according to the buzzer
Near, it will also send a different frequency of sound. (2017-10-10, Verilog, 12166KB, 下载1次)