本设计是基于单片机的锅炉水温控制，在设计中主要有按键控制、水温控制显示部分、故障报警等几部分组成来实现供暖控制。主要用热电阻传感器检测水温，用2个LED灯来进行温度报警，当水温超过设置的最高温限，则LED1灯亮起报警；当温度低于设置的最低温限，LED5灯亮起报警。本设计用单片机控制易于实现锅炉供暖、而且有造价低、程序易于调试、一部分出现故障不会影响其他部分的工作、维修方便、等优点。
This design is based on the single-chip microcomputer boiler water temperature control, in the design, there are key control, water temperature control display part, fault alarm and other parts to achieve heating control. It mainly uses the thermal resistance sensor to detect the water temperature, and uses two LED lights to give a temperature alarm. When the water temperature exceeds the set maximum temperature limit, LED1 lights up to give an alarm; when the temperature is lower than the set minimum temperature limit, LED5 lights up to give an alarm. This design is easy to realize boiler heating with single-chip microcomputer control, and has the advantages of low cost, easy debugging of program, one part of failure will not affect the work of other parts, convenient maintenance, etc. (2020-04-10, VHDL, 3014KB, 下载1次)
交通灯设计
基本要求：（1）设计一个交通红绿灯。要求分主干道和支干道，每条道上安装红（主：R,支：r）绿（主：G，支：g）黄（主：Y，支：y）三种颜色灯，由四种状态自动循环构成;
（2）在交通灯处在不同的状态时，设计一个计时器以倒计时方式显示计时，主干道上绿灯亮30S，支干道上绿灯亮20S。每个干道上，在绿灯转为红灯时，要求黄灯先亮5S。
Traffic light design
Basic requirements: (1) design a traffic light. The main main road and the trunk road are required, each road is installed red (Main: R, branch: R) green (Main: G, branch: G) yellow (Main: Y, branch: y) three kinds of color lights, composed of four states of automatic circulation;
(2) when the traffic lights are in different states, a timer is designed to show the timing by the way of countdown. The green light on the main road is bright 30S, and the green light on the branch road is 20S. On every main road, when the green light turns to a red light, the yellow light should be lit 5S first.
The decoded results are displayed at the target board as required. (2018-06-27, VHDL, 143KB, 下载1次)
? 1. Core加減器燒錄置板子照片(加法.減法)及測試結果。
? 2. 透過 Clock Wizard產生50Mhz、10Mhz及5Mhz頻率，並將測試結果上
傳。
3. 嘗試將Clock 及 加減模組同時引用，並透過frq選擇頻率，並將測試結果上傳。
module myAdder (a, b, out, cout, mode, clk, frq, clko
);
Input [3:0]a, b;
Input clk, mode; //1: adder; 0:sub
Input [1:0]frq;
Output [3:0]out;
Output cout, clko;
Clok instance_name
// INST_TAG_END ------ End INSTANTIATION Template ---------
Assign clko = frq > 1 ? CLK_OUT3 : (frq > 0)? CLK_OUT2 : CLK_OUT1;
myAdder your_instance_name (
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
endmodule
module myAdder (a, b, out, cout, mode, clk, frq, clko
);
Input [3:0]a, b;
Input clk, mode; //1: adder; 0:sub
Input [1:0]frq;
Output [3:0]out;
Output cout, clko;
Clok instance_name
// INST_TAG_END ------ End INSTANTIATION Template ---------
Assign clko = frq > 1 ? CLK_OUT3 : (frq > 0)? CLK_OUT2 : CLK_OUT1;
myAdder your_instance_name (
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
endmodule (2018-01-07, VHDL, 1KB, 下载1次)
编制一全双工UART电路，通过试验箱MAX202E转换成RS232电平，与计算机进行通讯实验，设置8个按键，按键值为ASIC码“1”~“8”，通过串口发送给计算机，在计算机上显示键值，同时在数码管最高位显示；计算机可发送“0”~“F”的ASIC码，FPGA接收后在数码管低位显示0~F。通过按键可设置波特率。
要求：波特率为三种 1200、2400、9600，由1个按键选择，3个LED分别指示；
数据格式为1位起始位、8位数据位和一位停止位；
上位计算机发送接收软件可使用“串口调试器“软件；
发送和接收数据时，由两个LED分别指示。
发挥：自动回发功能、接收到特殊字符（自定义）自动更改波特率。
A full duplex UART circuit, converted into RS232 level by MAX202E test box, communication experiment with computer, set of 8 buttons, keys for ASIC code "1" to "8", to the computer through the serial port to send and display keys on the computer, at the same time in the digital tube display high computer can send "; 0" to "F" in the ASIC code, FPGA after receiving the digital tube display low 0~F. You can set the baud rate by the button.
Requirements: baud rate for three, 1200, 2400, 9600, selected by 1 buttons, 3 LED, respectively;
The data format consists of 1 bit start bits, 8 bit data bits, and one stop bit;
The upper computer sends and receives the software, and the serial debugger can be used;
When sending and receiving data, instructions are given by two LED respectively.
Play: Auto postback function, receive special characters (custom), change baud rate automatically. (2017-06-16, VHDL, 2879KB, 下载1次)
基于FPGA闹钟系统的设计。
1.秒模块实际上是一个计数器，一秒记录一次并输出。
2.分，时模块在一个脉冲上升沿计数一次的基础上，加入了时间调整控制。
3.调整时间的控制模块，在使能信号有效时，才可实现时分的调整。
4.闹钟调整及控制模块，可实现闹钟设时的调节功能。
5.显示模块，实现时间与闹钟显示的切换。
6.闹铃模块，实现闹铃的发声装置。
7.总逻辑模块，实现电子闹钟相应功能的总系统。
FPGA-based alarm system design. 1. Second module is actually a counter, a second recording and output. 2. Am, when the module is a pulse based on the rising edge of a count by adding the time to adjust control. 3. Adjust the time of the control module, the enable signal is active in order to achieve the hours of adjustments. 4. Alarm clock adjustment and control modules can be realized when the alarm clock set up regulatory function. 5. Display module to realize the time and alarm clock display switch. 6. Alarm module to achieve the alarm audible signal devices. 7. The total logic block to realize the corresponding function of the total electronic alarm system. (2009-12-30, VHDL, 193KB, 下载6次)
8位单片机与DS18B20并行双向通信。
Quartus II 8.1项目工程文件.
主源程序文件为DS18B20.v,里面有详细注解。
例子：
DS18B20 数据地址 0xf000（ROM=0） DS18B20 ROM指令地址 0xf001（ROM=1）
外部电源供电且只有一DS18B20的读取法：
发送CC到0xf001,
等待busy=0说明器件已准备好,
读0xf001的Bit1=1说明存在器件,Bit0=1为控制忙(可以省略此步）
发送44到0xf000,
等待busy=0，
发送CC到0xf001，
等待busy=0，
发送BE到0xf000，
等待busy=0，
空读一次，
等待busy=0，
然后读到的就是DS18B20内部数据了.读一次必须等待busy=0，否则控制器将拒绝所有操作。
搜索ROM：
发送F0或EC到0xf001,
等待busy=0说明器件已准备好,
读0xf001的Bit1=1说明存在器件,Bit0=1为控制忙(可以省略此步）
空读0xf000，（第1次）
等待busy=0，
读0xf000，Bit0是DS18B20发送位的信息，Bit1为DS18B20发送位的补码信息
等待busy=0，
写0xf000，内容为路径。
等待busy=0，
。。。。。。
空读0xf000，（第64次）
等待busy=0，
读0xf000，Bit0是DS18B20发送位的信息，Bit1为DS18B20发送位的补码信息
等待busy=0，
写0xf000，内容为路径。
等待busy=0，
结束
8-bit microcontroller with DS18B20 parallel two-way communication.
Quartus II 8.1 Project documents.
Primary source documents DS18B20.v, which detailed notes.
Example:
DS18B20 Data Address 0xf000 (ROM = 0) DS18B20 ROM instruction address 0xf001 (ROM = 1)
An external power supply and only a DS18B20 read method:
Send CC to 0xf001,
Wait for busy = 0 shows the device is ready,
Read 0xf001 the existence of Bit1 = 1 shows the device, Bit0 = 1 for the control of busy (you can omit this step)
Send 44 to 0xf000,
Wait for busy = 0,
Send CC to 0xf001,
Wait for busy = 0,
Send BE to 0xf000,
Wait for busy = 0,
Blank reading time,
Wait for busy = 0,
Then read is DS18B20 internal data. Read one must wait for the busy = 0, otherwise the controller will reject all operations.
Search ROM:
Send F0 or EC to 0xf001,
Wait for busy = 0 shows the device is ready,
Read 0xf001 the existence of Bit1 = 1 shows the device, Bit0 = 1 for the control of busy (you can omi (2009-12-06, VHDL, 331KB, 下载15次)
利用VHDL设计的另外一种方法的交通灯程序。在controller模块中设置了2个进程，其中一个用来控制内置计数器的增加，一个用来控制交通灯的显示。从controller模块中出来的时间是2位的BCD码，要进行数码管显示就需要得到2个一位的BCD码，因此就需要利用separate模块来实现。separate模块的思想也比较简单，就是利用比较然后得到相应的十位数和个位数。
In the controller module set up two processes, one of which is used to control the built-in counter the increase in one is used to control the traffic light display. From the controller module out of time is 2-bit BCD code to a digital LED display on the need to be two of a BCD code, and therefore need to use separate modules to achieve. separate module' s thinking was relatively simple, is to use more then the corresponding 10-digit and single digits. (2009-11-26, VHDL, 13KB, 下载2次)