联合开发网   搜索   要求与建议
                登陆    注册
排序按匹配   按投票   按下载次数   按上传日期
按分类查找All VHDL/FPGA/Verilog(362) 
按平台查找All matlab(362) 

[VHDL/FPGA/Verilog] Design-and-Verification-of-LDPC-Decoder-master

利用最小和法在Matlab中设计LDPC解码器。
Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab. (2020-05-12, matlab, 135KB, 下载3次)

http://www.pudn.com/Download/item/id/1589276992441745.html

[VHDL/FPGA/Verilog] abc

运行一个Matlab程序,完成一个M=4的PAM通信系统的仿真。仿真对10000个符号(2万个比特)进行。测量在噪声方差为0,0.1,1.0和2.0时的符号差错概率。通过低通滤波器。画出理论误码率和由Monte Carlo仿真测得的误码率,并比较这些结果。(平均符号能量为1)
Running a Matlab program, complete a M = 4 PAM communication system simulation. The simulation of 10000 symbols (20000 bits). Measurement in the noise variance is 0,0.1, 1.0 and 2.0 when the symbol error probability. Through the low pass filter. Draw the theoretical error rate and Monte Carlo simulation by measured error rate, and compare these results. (average symbol energy for 1) (2012-12-03, matlab, 1KB, 下载26次)

http://www.pudn.com/Download/item/id/2069542.html
总计:362