在基于MicroBlaze AXI软核的FreeRTOS上运行的闭环PID控制器与MPU-6050加速度计陀螺仪模块接口。
A closed loop PID controller running on FreeRTOS on MicroBlaze AXI based soft core interfaced with a MPU-6050 Accelerometer Gyroscope module. (2024-03-04, Verilog, 0KB, 下载0次)
该项目涉及设计和实现具有5级流水线的32位MIPS RISC处理器。它提供了一个宝贵的机会...，
This project involves designing and implementing a 32-bit MIPS RISC processor with a 5-stage pipeline. It offers a valuable opportunity to gain knowledge in hardware design and computer architecture concepts. Implemented the processor in a hardware description language Verilog. (2023-08-12, Verilog, 0KB, 下载0次)
创建了一个具有8个寄存器和16位总线的CPU模型。支持8个功能：lie、ADD、SUB、MULT、JUMP。接收到来自ROM存储的信息...，
Created a model CPU with 8 registers and a 16-bit bus. Supports 8 functions lie, ADD, SUB, MULT, JUMP. Recieved information from ROM storage and a program conter. Supports FPGA. (2023-08-08, Verilog, 0KB, 下载0次)
基于单周期MIPS的处理器体系结构，作为计算机体系结构和组织实验室的最终项目设计...，
Single-cycle MIPS-based processor architecture, designed as the final project for the Laboratory of Computer Architecture and Organization course and later enhanced for both Laboratory of Operational Systems and Laboratory of Computer Networks courses. (2019-07-25, Verilog, 0KB, 下载0次)
32位流水线MIPS处理器的Verilog代码。带有控制信号的数据路径图包含在PDF格式中。门-...的组合...，
Verilog code for a 32-bit pipelined MIPS processor. Datapath diagram with control signals is included in PDF format. Combination of gate-level, dataflow and behavioural modelling. Remarks: Instruction Memory for 32 32-bit MIPS instructions. 32 32-bit Data Memory locations. Instruction Memory consisting of arithmetic, logical, branch, jump, and (2020-09-07, Verilog, 0KB, 下载0次)
一个粗糙而简单（但可以工作！）的MIPS处理器，用Verilog编写，设计用于在DE 2板（Cyclone II FPGA）上实现，
A crude and simple (but working!) MIPS processor, written in Verilog and designed for implementation on a DE 2 board (Cyclone II FPGA), (2014-02-27, Verilog, 0KB, 下载0次)
基于MIPS32指令集(部分指令)的五级流水线CPU。验证方法:使用指令跑通了斐波那契数列(可用寄存器指定项数)。,
Five stage pipelined CPU based on MIPS32 instruction set (partial instructions). Verification method: The Fibonacci number sequence was run through with instructions (the number of items can be specified in the register)., (2020-03-08, Verilog, 0KB, 下载0次)
FPGA(现场可编程门阵列)与 CPLD(复杂可编程逻辑器件)都是可编程逻辑器件，它们是在PAL,GAL等逻辑器件的基础之上发展起来的。同以往的PAL,GAL等相比较，FPGA／CPLD的规模比较大，它可以替代几十甚至几千块通用IC芯片。这样的FPGA／CPLD实际上就是一个子系统部件。
本次EDA课程设计就是利用VerilogHDL来设计设计一个2选1多路选择器
FPGA (field programmable gate array) and CPLD (complex programmable logic device) are programmable logic devices. They are developed on the basis of pal, gal and other logic devices. Compared with pal and gal, FPGA / CPLD has a large scale and can replace dozens or even thousands of general IC chips. Such FPGA / CPLD is actually a subsystem component.
This EDA course design is to use Verilog HDL to design a 2-out-of-1 multiplexer (2020-05-11, Verilog, 1KB, 下载0次)
FPGA(现场可编程门阵列)与 CPLD(复杂可编程逻辑器件)都是可编程逻辑器件，它们是在PAL,GAL等逻辑器件的基础之上发展起来的。同以往的PAL,GAL等相比较，FPGA／CPLD的规模比较大，它可以替代几十甚至几千块通用IC芯片。这样的FPGA／CPLD实际上就是一个子系统部件。
本次EDA课程设计就是利用VerilogHDL来设计设计一个4位加法器
FPGA (field programmable gate array) and CPLD (complex programmable logic device) are programmable logic devices. They are developed on the basis of pal, gal and other logic devices. Compared with pal and gal, FPGA / CPLD has a large scale and can replace dozens or even thousands of general IC chips. Such FPGA / CPLD is actually a subsystem component.
This EDA course design is to use Verilog HDL to design a 4-bit adder (2020-05-11, Verilog, 1KB, 下载0次)
利用 CPLD 器件和实验开发板，设计并实现一个抽油烟机控制器.1．抽油烟机的基本功能只有两个：排油烟和照明，两个功能相互独立互不影响。
2．用 8×8 双色点阵模拟显示烟机排油烟风扇的转动，风扇转动方式为如图所示的四个 点阵显示状态，四个显示状态按顺序循环显示。风扇转动速度根据排油烟量的大小 分为 4 档，其中小档的四个显示状态之间的切换时间为 2 秒，中档为 1 秒，大档为 0.5 秒，空档时风扇静止不动（即停止排油烟），通过按动按键 BTN6来实现排油烟 量档位的切换，系统上电时排油烟量档位为空档，此后每按下按键 BTN6一次，排油烟量档位切换一次，切换的顺序为：空档→小档→中档→大档→空档，依次循环。
Using CPLD device and experimental development board, a controller of the range hood is designed and implemented. (2019-11-19, Verilog, 6847KB, 下载0次)
滤波器就是对特定的频率或者特定频率以外的频率进行消除的电路，被广泛用于通信系统和信号处理系统中。
Filter is a circuit that eliminates specific frequencies or frequencies other than specific frequencies. It is widely used in communication systems and signal processing systems. (2019-07-27, Verilog, 12KB, 下载1次)
设计一个可容纳4组参赛的数字式抢答器，每组设一个按钮，供抢答使用。??
1、抢答器具有第一信号鉴别和锁存功能，使除第一抢答者外的按钮不起作用。??
2、设置一个主持人“复位”按钮。??
3、主持人复位后，开始抢答，第一信号鉴别锁存电路得到信号后，有指示灯显示抢答组别。
Design a digital responder which can accommodate 4 groups of entries. Each group has a button for answering. Such
1, the responder has the first signal identification and latching function, so that the button outside the first responder will not work. Such
2, set up a host "reset" button. Such
3. After the host reset, the responder begins to answer. After the first signal identification latch circuit gets the signal, there is an indicator light showing the answer group. (2018-06-22, Verilog, 313KB, 下载0次)
TSM该系列产品内部集成有一个电压基准器件和两个运算放大器，电压基准器件和一个运算放大器的集成构成理想的电压控制器；另外一个运算 放大器再与这个集成的电压基准器件和几个外部电阻器配合，起到限流器的作用。该类IC广泛用于需要恒压(CV)和恒流（CC）模式的开关电源中，如要求恒 压和输出限流的充电器及适配器中
Both TSM103 and TSM103A belong to the TSM10X series. The series of products are integrated with a voltage reference device and two operational amplifiers. The integration of voltage reference and an operational amplifier constitutes an ideal voltage controller; the other operational amplifier works with the integrated voltage reference device and several external resistors to play the role of the current limiter. This type of IC is widely used in switching power supply with constant voltage (CV) and constant current (CC) mode, such as the charger and adapter that require constant voltage and output current limiting. (2018-04-27, Verilog, 160KB, 下载1次)
功能
多路外部信号选通输入到LED显示
读取当前LED显示状态
PB or SW
通过标志寄存器配置
function
Multiple external signals are selected to be input to LED display
Read the current LED display status
PB or SW
Flag register configuration (2017-12-07, Verilog, 1414KB, 下载2次)
用FPGA开发板的按键作为电子表的时间初值设置控制信号，数码管当前时间值输出。用按键选择分别输出：分、秒、1/10秒。
With FPGA development board button, as the time value of the electronic table, set the control signal, digital tube current time value output. Select output by buttons: minutes, seconds, and 1/10 seconds. (2017-10-11, Verilog, 331KB, 下载2次)
可以实现n+0.5倍的分频，本程序是利用50MHz的FPGA开发板实现分别实现10MHz，2.5MHz的分频时钟。
N+0.5 times can be achieved frequency division, this procedure is to use 50MHz FPGA development board to achieve, respectively, 10MHz, 2.5MHz frequency division clock. (2017-07-25, Verilog, 3117KB, 下载2次)