[汇编语言] new 33
epprom读写器实现数据的读写操作，实现IIC功能，可以用
EPPROM reader and writer (2018-05-10, VHDL, 1KB, 下载0次)
[汇编语言] fazhi
这是一个将模拟量转换成数字量的VHDL源代码，能够转换正弦波，三角波，方波；通过设定一个阀值，再用比较器比较实现的！
This is an analog quantity into a digital representation of the VHDL source code, to convert sine wave, triangle wave, square wave by setting a threshold, then comparator compares the implementation! (2010-04-07, VHDL, 469KB, 下载3次)
[汇编语言] course-design-cpu-poc
满足并行输出输入的功能，同时与打印机相连，程序中又添加了微处理器的程序。
To meet the parallel input-output function, while with the printer connected to the program has added a microprocessor program. (2010-03-10, VHDL, 1719KB, 下载6次)
[汇编语言] seg7_counter
這是一個提供上下數的七段顯示器之verilog的程式。透過此程式可簡易的學習如何撰寫程式來控制七段顯示器。
This is a seven-segment display to provide the upper and lower number of verilog program. Through this program can be simple to learn how to write programs to control the seven-segment display. (2010-02-25, VHDL, 1KB, 下载4次)
[汇编语言] luo
瑞萨单片机相关寄存器的设置与代码！编程，C语言！仅供参考！
,jbjhfmk (2010-01-10, VHDL, 523KB, 下载7次)
[汇编语言] D
实现了程序控制的反馈移位寄存器，包括开关防抖，时钟整形，移位，和码型控制
Achieve program control of the feedback shift register, including anti-shake switch, clock shaping, shift, and code-mode control (2009-12-24, VHDL, 1KB, 下载27次)
[汇编语言] regheap_v
该模块实现一个寄存器堆的操作，其中前16个仅主机能写，规给为32-bit×32。后16个仅Micorblaze能写。读取没有限制。如果双方同时对同一地址进行读写操作，读回的数将是全1。
This module implement a register file of the operation, of which the first host 16 is only able to write rules to the 32-bit × 32. Micorblaze only 16 after the write. There is no limit to read. If the two sides at the same time to read and write operations to the same address, read back would have been a full one. (2009-12-10, VHDL, 2KB, 下载6次)
[汇编语言] 8weishijinzhijishuqi
一个简单的8位十进制计数器源代码，VHDL实现编程
A simple 8-bit decimal counter source code, VHDL realization of programming (2009-12-07, VHDL, 230KB, 下载7次)
[汇编语言] l7
使用VHDL语言编写的简易数字存储示波器，用MAX+PlusII仿真验证。VHDL编写了采样、存储写、存储读和显示4个模块。采样使用ADC0809，存储器使用6264，显示使用DAC0832。-The design of the chip as a high-speed signal ADC0809 the A / D converter, SRAM6264 memory for data storage after sampling, DAC0832 chip as a signal of D / A conversion. Programming using ultra-high-speed hardware description language VHDL description of its A / D conversion, A / D sampling controller and data storage, digital output programming, simulation, the completion of the design of hardware and software, as well as some of the experimental prototype debugging
DAC0832。-The design of the chip as a high-speed signal ADC0809 the A/D converter, SRAM6264 memory for data storage after sampling, DAC0832 chip as a signal of D/A conversion. Programming using ultra-high-speed hardware description language VHDL description of its A/D conversion, A/D sampling controller and data storage, digital output programming, simulation, the completion of the design of hardware and software, as well as some of the experimental prototype debugging (2009-11-23, VHDL, 145KB, 下载35次)
[汇编语言] FIRfenbushisuanfa
基于分布式算法数字滤波器 VHDL语言编写 适用于FPGA
Digital filters based on distributed algorithms written in VHDL for FPGA (2009-09-18, VHDL, 2642KB, 下载9次)
[汇编语言] 64_TLC
交通灯控制器
请注意:
本例的各个源描述的编译顺序应该是:
64_tlc.vhd
64_test_vector.vhd
Traffic Light Controller Please note: This case is described in various sources to compile the order should be: 64_tlc.vhd 64_test_vector.vhd (2009-09-04, VHDL, 2KB, 下载7次)
[汇编语言] I2C
用verilog编写的驱动I2C接口的存储器pca9534的程序运行成功
Prepared using verilog memory-driven I2C interface of the program to run successfully pca9534 (2009-06-29, VHDL, 344KB, 下载8次)
[汇编语言] second
上传个EDA得VHDL语言编程得秒计时器，希望对大家能有所帮助 谢谢了
From months EDA was VHDL language programming a second timer, I hope all of you can help I would like to thank the (2008-12-30, VHDL, 3KB, 下载46次)
[汇编语言] cntm9999
一个至少4位的十进制计数器，具有加减计数功能和置数功能，并能通过数码管显示计数结果。减数为零时发声报警。
At least four decimal counter with addition and subtraction functions and buy a few counting function, and can count the results of digital tube display. Decreases to zero when the audible alarm. (2008-12-18, VHDL, 1KB, 下载16次)
[汇编语言] zhiliqiangdaqi
可以供四组人员进行操作的智力抢答器，当一次抢答完成后可以复位继续进行抢答，当抢答成功时会显示号码并响铃
Be available for four groups of personnel to operate the intellectual Answer, and when after the completion of an Answer to Reset Answer to continue, when the Answer success will show number and ringing (2008-10-30, VHDL, 2KB, 下载13次)
[汇编语言] balucaidengkongzhiqi
一个八路彩灯控制器,3种花型（便于修改）、两种频率交替进行
An eight-way controller Lantern, 3 flower-type (easy to modify), two frequency alternating (2008-10-30, VHDL, 1KB, 下载24次)
[汇编语言] VHDLjianfaqi
这是一个利用MAX PULL 制作的VHDL的减法器的程序 如果有需要仿真图的 请叫站长联系我
This is a MAX PULL produced using VHDL s process of subtraction, if necessary simulation diagram contact me please call station (2008-06-14, VHDL, 1KB, 下载7次)
[汇编语言] VHDLsiweichufaqi
这是一个利用MAX PULL 制作的VHDL的四位除法器的程序 如果有需要仿真图的 请叫站长联系我
This is a MAX PULL produced using VHDL divider of the four procedures, if necessary simulation diagram contact me please call station (2008-06-14, VHDL, 2KB, 下载8次)
[汇编语言] VHDLquanjiaqi
这是一个利用MAX PULL 制作的VHDL的全加器的程序 如果有需要仿真图的 请叫站长联系我
This is a MAX PULL produced using the full adder VHDL process simulation map, if necessary please contact me call station (2008-06-14, VHDL, 1KB, 下载1次)
[汇编语言] 66_FIR
使用硬件实现,效率较高的滤波器,通过FPGA验证的
The use of hardware implementation, high efficiency filter, through the FPGA verification (2008-04-05, VHDL, 8KB, 下载11次)