这是一个用verilog设计的尖峰神经网络，该网络采用izhekevich神经元作为神经元模型，用aer控制器进行通信...，
This is a spiking neural network designed in verilog, This netwoek used izhekevich neuron as as neuron model and aer controller for communication, and BCM block for learning. (2023-06-12, Verilog, 0KB, 下载0次)
ReckOn:一种Spiking RNN处理器，可在第二长时间范围内实现片上学习-HDL源代码和文档...
ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation. (2022-02-18, Verilog, 318KB, 下载0次)
OpenMIPS,计算机组成原理课程设计内容,设计一个兼容MIPS32指令集架构的处理器——OpenMIPS(五级流水结构),并增加IO模块(人机交互式),解决数据依赖问题
OpenMIPS, course design content of computer composition principle, design a processor compatible with MIPS32 instruction set architecture - OpenMIPS (five level pipeline structure), and add IO module (human-computer interaction) to solve the problem of data dependence (2020-06-24, Verilog, 2557KB, 下载0次)
依赖SDRAM的图像系统，一种基于自主SDRAM的实时图像采集系统，使用自动读写FIFO和VGA驱动器
SDRAM-dependent-image-system,A real-time image acquisition system based on autonomous SDRAM, using automatic read-write FIFO and VGA drivers (2023-02-07, Verilog, 2795KB, 下载0次)
polyphase_filter_prj,哈工大软件无线电课设:多相滤波器的原理、实现及其应用,从采样率变换、多相滤波器结构到信道化收发机应用都有matlab介绍和FPGA仿真结果,含答辩PPT、学习笔记和个人总结。
polyphase_ filter_ PRJ, Software Radio Course Design at Harbin Institute of Technology: The principle, implementation, and application of polyphase filters, from sampling rate conversion, polyphase filter structure to channelized transceiver applications, all have Matlab introductions and FPGA simulation results, including defense PPTs, study notes, and personal summaries. (2017-04-19, Verilog, 35965KB, 下载1次)
wut-FPGA-simpleCNN,这是武汉理工大学集创赛初赛工程,选题基于FPGA的简易神经网络加速器
Wut-FPGA-simpleCNN, this is the preliminary project of Wuhan University of Technology Innovation Competition, and the topic is based on a simple neural network accelerator using FPGA (2023-02-27, Verilog, 45KB, 下载0次)
cnn_accelerator,【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器
cnn_ Accelerator, [Introduction Project] Hardware accelerator of convolutional neural network for handwritten digit recognition based on PYNQ-Z2 (2023-04-10, Verilog, 49552KB, 下载4次)
CFU游乐场，想要更快的ML处理器自己动手！——一个使用自定义操作码加速TensorFlow L的框架...
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: <https://google.github.io/CFU-Playground/> For reference docs, see the link below. (2023-04-25, Verilog, 13257KB, 下载0次)