调制和任意波形发生器
Modulation and Arbitrary Waveform Generator (2021-02-16, Verilog, 31KB, 下载0次)
信号发生器DDS，小梅哥精品课程案例，可输出独立的4路正弦信号
Signal generator DDS, xiaomeige excellent course case, can output independent 4-way sine signal (2021-03-17, Verilog, 1069KB, 下载0次)
FGPA关于DDS信号发生器的开源程序，已实现modelsim仿真 ，附带仿真程序
FGPA DDS signal generator on the open source program, has been achieved Modelsim simulation, with simulation procedures (2021-01-17, Verilog, 5812KB, 下载2次)
实现数字频率合成实验，加载数据ram,形成波形
The experiment of digital frequency synthesis is realized, and the data RAM is loaded to form the waveform (2020-11-10, Verilog, 26282KB, 下载2次)
dds 直接频率生成 工程 代码 源文件
DDS direct frequency generation of engineering code source file (2020-09-16, Verilog, 11143KB, 下载1次)
基于fpga的信号发生器，通过调整按键可以生成正弦波，方波，三角波，锯齿波
Sine wave, square wave, triangular wave, sawtooth wave (2020-07-19, Verilog, 15940KB, 下载4次)
读取单片机写入的控制字，将其写入DDS的寄存器
Read the control word written by MCU and write it into the register of DDS (2020-04-26, Verilog, 6KB, 下载4次)
可以产生最基本的三角波，正弦波，方波信号，比较简单
You can generate triangular wave, sine wave, square wave signals (2020-03-13, Verilog, 1KB, 下载1次)
基于PCF8591数模转换和DDS技术的信号发生器系统设计
Design of Signal Generator System Based on PCF8591 Digital-to-Analog Conversion and DDS Technology (2019-07-29, Verilog, 359KB, 下载3次)
FPGA做波形发生器，产生8种波形，包括三角波，正弦波，锯齿波，方波等。
FPGA is used as waveform generator,Generate 8 waveforms, including triangle, sine, sawtooth, square, etc. (2019-07-16, Verilog, 2035KB, 下载4次)
任意波形发生器的频率控制字部分，ISE编写的一个verilog程序。
The frequency control word portion of the arbitrary waveform generator, a verilog program written by ISE. (2019-04-10, Verilog, 173KB, 下载0次)
基于FPGA 的VGA波形显示，dds产生三角波正弦波
Vga waveform display based on FPGA, using DDS to generate sinusoidal triangular wave (2018-12-12, Verilog, 21085KB, 下载6次)
verilog生成DDS,并且具有调幅度的功能，需要有DAT文件。
Verilog generates DDS, and has the function of amplitude modulation. It needs DAT files. (2018-10-14, Verilog, 13266KB, 下载0次)
通过按键控制产生任意频率的方波，正弦波，三角波，锯齿波
Fang Bo, sine wave, triangle wave and sawtooth wave at any frequency are generated by key control (2018-07-08, Verilog, 4042KB, 下载6次)
DDS生成正弦波和方波，其中正弦波调用rom的ip核进行查表产生波形，方波直接用计数器counter生成。时钟通过PLL ip核进行分频。使用中注意我的是quartus15.1，别的版本打开文件可能要重建IP核，其中ROM对应的.v文件中的数据文件的绝对地址要改，改成你的就行。
DDS generates sine wave and Fang Bo, where the sine wave calls the IP core of ROM to look up the table to generate waveform, and the square wave is generated directly by counter counter. The clock is divided by the PLL IP core. In the use of my attention is quartus15.1, other versions of the open file may be to rebuild the IP core, of which the ROM corresponding to the.V file of the absolute address of the data file to change to your right. (2018-06-14, Verilog, 8456KB, 下载3次)
dds算法，调用xilinx IP ，ise
DDS algorithm, call Xilinx IP, ISE (2018-04-17, Verilog, 5594KB, 下载8次)
实现了DDS的verilog源代码，可以使用
ajhsjdhjkshfjhfsjkjksa (2018-02-27, Verilog, 3KB, 下载3次)
dds输出一个正弦波，通过修改频率控制字来控制频率
DDS outputs a sine wave to control frequency by modifying the frequency control word (2017-11-27, Verilog, 5437KB, 下载7次)
可以实现DDS 的正负线性扫频以及在线参数设置
DDS ad9914/ad9915 code (2017-10-23, Verilog, 5KB, 下载30次)
基于FPGA的DDS正弦信号设计，文件中有源代码
Design of DDS based on FPGA (2017-08-06, Verilog, 50KB, 下载11次)