FIFO（First?In?First?Out，即先入先出），是一种数据缓冲器，用来实现数据先入先出的读写方式。
FIFO (first in first out) is a data buffer, which is used to read and write data first in first out. (2021-04-20, Quartus II, 6140KB, 下载0次)
121奥术大师大所多撒大所多a's萨达所大
who is your daddy and why (2020-10-22, Quartus II, 221KB, 下载0次)
清华大学EDA大作业1，可以实现两个范围为-3到3的整数相加
Tsinghua University EDA homework 1 can add two integers in the range of - 3 to 3 (2019-12-14, Quartus II, 629KB, 下载0次)
十二进制加减法可逆的计数器，新手入门可用
A reversible counter for addition and subtraction in hexadecimal. It is available for beginners (2019-12-09, Quartus II, 1KB, 下载0次)
Create a new Quartus Prime project with top level entity named mux2_1_struct and select the appropriate target device
Create a new Quartus Prime project with top level entity named mux2_1_struct and select the appropriate target device (2019-11-24, Quartus II, 1043KB, 下载0次)
FPGA上实现的的分频器，Quartus II平台，VHDL语言
The frequency divider implemented on FPGA, Quartus II platform, VHDL language. (2018-05-18, Quartus II, 102KB, 下载0次)
熟悉使用1602液晶显示器，用28335控制1602，各个引脚怎样配置
Be familiar with the use of 1602 liquid crystal displays, control 1602 with 28335, and how to configure each pin (2018-01-30, Quartus II, 86KB, 下载4次)
利用EDA的Quartus2语言，实现三进八出的译码等功能。
The use of EDA Quartus2 language, to achieve three out of the eight decoding function. (2018-01-23, Quartus II, 26KB, 下载1次)
利用EDA的Quartus2语言，实现四进一出的译码等功能。
Using the Quartus2 language of EDA, the function of decoding the four into one is realized. (2018-01-23, Quartus II, 78KB, 下载1次)
串行转并行,spi串口协议，移位寄存器模块，时钟模块，宏定义参数模块
Serial parallel, SPI serial protocol, shift register module, clock module, macro definition parameter module (2017-12-17, Quartus II, 447KB, 下载1次)