DDS波形发生器下载搜索联合开发网

[VHDL/FPGA/Verilog] axi-timer

这是Xilinx AXI定时器的说明手册，对于进行FPGA开发的工程师有参考价值
The LogiCORE IP AXI Timer/Counter is a 32/ 64-bit timer module that interfaces to the AXI4-Lite interface. (2016-08-02, Unix_Linux, 424KB, 下载2次)

http://www.pudn.com/Download/item/id/1470116680765423.html

[VHDL/FPGA/Verilog] FlyCounter11

一个非常简单的计数器，带8种计数器图片。可统计总访问量，每日访问量可设置以文字方式显示或图片方式显示不防刷新。不计IP
A very simple counter with eight counter image. It counts the total number of visits, daily visits It can be set to display text or image display Not anti refresh. Excluding IP (2016-03-07, Unix_Linux, 57KB, 下载1次)

http://www.pudn.com/Download/item/id/1457355329109863.html

[VHDL/FPGA/Verilog] a_vhd_16550_uart_latest.tar

这个芯的设计是与国家半导体PC16550D兼容 UART（通用异步接收器/发送器）。一些差异：该FIFO的始终启用不支持置顶奇偶
This core is designed to be a compatible with the National Semiconductor PC16550D UART (Universal Asynchronous Receiver/Transmitter).Some differences: The FIFO’s are always enabled Sticky Parity is not supported (2015-09-13, Unix_Linux, 117KB, 下载3次)

http://www.pudn.com/Download/item/id/1442109069908267.html

[VHDL/FPGA/Verilog] SDRAM_Memoy

SDRAM动态存储器在视频监控中的设计与实现。实现3D DCT视频压缩系统。
SDRAM, 3D DCT (2014-06-13, Unix_Linux, 122KB, 下载2次)

http://www.pudn.com/Download/item/id/2566929.html

[VHDL/FPGA/Verilog] FIFO

FIFO，先进先出缓冲器，verilog源代码，包括测试代码。
FIFO, FIFO buffer, verilog source code, including test code. (2014-05-12, Unix_Linux, 2KB, 下载7次)

http://www.pudn.com/Download/item/id/2538362.html

[VHDL/FPGA/Verilog] FIFO

客户进程-服务器通信，用于学习FIFO进程间通信
cilent-sever-FIFO,linux code (2014-04-11, Unix_Linux, 11KB, 下载2次)

http://www.pudn.com/Download/item/id/2508673.html

[VHDL/FPGA/Verilog] shiyanqdq

基于FPGA 实现的4人抢答器模块的基础源程序。
FPGA-based realization of four Responder module (2013-05-29, Unix_Linux, 851KB, 下载2次)

http://www.pudn.com/Download/item/id/2262232.html

[VHDL/FPGA/Verilog] ARM2440tested-sucess

将代码下载到ARM9中进行测试,包括lcd,led,adc,蜂鸣器
To download code to ARM9 test (2013-04-20, Unix_Linux, 19KB, 下载3次)

http://www.pudn.com/Download/item/id/2208603.html

[VHDL/FPGA/Verilog] 4M_CFE

路由系统CPU305X 编程器用CFE 可刷ＴＴ，ＯＰ，ＤＤ
The routing system CPU305X programmer with CFE (2013-01-05, Unix_Linux, 68KB, 下载2次)

http://www.pudn.com/Download/item/id/2106983.html

[VHDL/FPGA/Verilog] FIR_filter

用powerpoint介绍了FIR滤波器的设计，简洁明了，学习方便。
FIR filter design using powerpoint, concise and convenient learning. (2012-10-23, Unix_Linux, 2271KB, 下载4次)

http://www.pudn.com/Download/item/id/2024787.html

[VHDL/FPGA/Verilog] decimetion

攒人品上传多年工作积累代码。主要功能是adc 的多阶后续数字滤波器，等控制。可以综合。
Save the character to upload the accumulation of many years of working code. The main function is to adc the multi-order follow-up digital filter control. Can be integrated. (2012-07-08, Unix_Linux, 35KB, 下载8次)

http://www.pudn.com/Download/item/id/1933431.html

[VHDL/FPGA/Verilog] decoder_3_8

基于verilog的38译码器，八个输出，三个输入
counter based on verilog (2011-12-30, Unix_Linux, 1145KB, 下载5次)

http://www.pudn.com/Download/item/id/1747143.html

[VHDL/FPGA/Verilog] mips_core

mips的一个模型,基本实现了mips处理器功能
a model for mips cpu。 (2011-01-25, Unix_Linux, 1KB, 下载2次)

http://www.pudn.com/Download/item/id/1419694.html

[VHDL/FPGA/Verilog] ARM7andFPGA

基于ARM7与FPGA组成的可编程控制器
Based on the composition of ARM7 and FPGA programmable logic controller (2009-10-15, Unix_Linux, 357KB, 下载4次)

http://www.pudn.com/Download/item/id/938888.html

[VHDL/FPGA/Verilog] ovm-1[1].0.1.tar

ovm 公开的源代码，用于asic设计验证，但要ncverilog的仿真器一起用
ovm verfication package (2009-08-21, Unix_Linux, 738KB, 下载7次)

http://www.pudn.com/Download/item/id/885030.html

[VHDL/FPGA/Verilog] dividers

verilog格式的除法器，试过了，很好用，再也不要为触发器发愁了
Verilog format divider, tried, very good, and no longer for the flip-flop not to worry about the (2009-03-11, Unix_Linux, 10KB, 下载211次)

http://www.pudn.com/Download/item/id/668583.html

[VHDL/FPGA/Verilog] single_clock_divider

单周期除法器，速度快，满足频率要求，使得单周期内得到除数
Single-cycle divider speed, to meet the frequency requirements (2009-03-11, Unix_Linux, 119KB, 下载41次)

http://www.pudn.com/Download/item/id/668578.html

[VHDL/FPGA/Verilog] traffic5

VHDL编写的异步通信控制器源代码程序
VHDL prepared by the asynchronous communication controller source code procedures (2007-04-25, Unix_Linux, 4KB, 下载23次)

http://www.pudn.com/Download/item/id/273232.html

[VHDL/FPGA/Verilog] veoghdl

用VHDL语言编写的异步通信控制器源代码程序
VHDL language of asynchronous communication controller source code procedures (2007-04-25, Unix_Linux, 62KB, 下载26次)

http://www.pudn.com/Download/item/id/273229.html

[VHDL/FPGA/Verilog] a VHDL Compiler

这是一个VHDL（硬件描述语言）的编译器，更确切说是一个解释器，输入是VHDL语言，输出是经过提到后的符号表，也就是将VHDL中的重要变量比如输入输出变量和DFF等保存下来。
This is a VHDL (hardware description language) compiler, more precise explanation is a device that is VHDL input, output was mentioned after the symbol table to VHDL is the important variables such as input and output variables and other DFF preserved. (2005-03-29, Unix_Linux, 115KB, 下载14次)

http://www.pudn.com/Download/item/id/1112066003665580.html