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[VHDL/FPGA/Verilog] baseed-on-EDA-of-three-BCD-counter

基于EDA的三位BCD计数器，实现从0到999的计数功能
based on EDA of three BCD counter (2017-05-06, WORD, 11827KB, 下载2次)

http://www.pudn.com/Download/item/id/1494040657754683.html

[VHDL/FPGA/Verilog] learning-diary

verilog编程经验，包括各种建模的区别各种会产生锁存器的操作分析等
tips for verilog program (2015-04-15, WORD, 182KB, 下载1次)

http://www.pudn.com/Download/item/id/1429083887965958.html

[VHDL/FPGA/Verilog] FPGADE270CACULATOR

本文介绍了一个简单的计算器的设计，该设计采用了现场可编程逻辑器件FPGA设计，并基于VHDL语言实现加减乘除功能，并用十进制显示在LCD1602上。
This article describes a simple calculator design that uses a field programmable logic device FPGA design and VHDL language based on arithmetic functions, and decimal display on LCD1602. (2014-04-05, WORD, 3319KB, 下载5次)

http://www.pudn.com/Download/item/id/2503034.html

[VHDL/FPGA/Verilog] fir_compiler_ds534

详细的描述了XILINX ISE软件里的IP核的内部结构。详细的介绍了滤波器的各个内部机构和各个功能。
A detailed description of the internal structure of the the XILINX ISE software IP core. Detailed introduction of various internal organs and the various functions of the filter. (2013-03-29, WORD, 1161KB, 下载43次)

http://www.pudn.com/Download/item/id/2178933.html

[VHDL/FPGA/Verilog] Matlab

MATLAB滤波器设计工具箱函数，相关指令
MATLAB filter design the toolbox functions related instruction (2012-11-26, WORD, 16KB, 下载8次)

http://www.pudn.com/Download/item/id/2061656.html

[VHDL/FPGA/Verilog] xp

96pin连接器、3366电位器、67148_AD_AD537、AD202隔离放大器、AD537、AD650SD电压频率,频率电压转换器、AD1671高速AD、AD7376,128位数字电位计、ADR440_441_443_444_445、CA3140高输入阻抗运算放大器、EPM7256,FPGA、IC封装大全、IRF430功率场效应管、LH0070、LM139四路差动比较器、MAX197、PCA82C250[1]、Pt1000、TD823高温功率放大器、TD823高温功率放大器、固态继电器AQZ264、DAC0832、LTC1859、LM124、dac0832、MAX1300-MAX1301、TLV5633的英文和中文资料
SCM, 96pin connector, 3366 potentiometer, 67148_AD_AD537, AD202 isolation amplifier, AD537, AD650SD voltage frequency, frequency-voltage converter, AD1671 high-speed AD, AD7376, 128-bit digital potentiometer, ADR440_441_443_444_445, CA3140 high input impedance operational amplifier, EPM7256, FPGA, IC packaging Daquan, IRF430 power FET, LH0070, LM139 quad differential comparator, MAX197, PCA82C250 [1], Pt1000, TD823 high power amplifier, TD823 high power amplifiers, solid state relays AQZ264, DAC0832, LTC1859, LM124, dac0832, MAX1300-MAX1301, TLV5633 information in English and Chinese (2011-09-20, WORD, 10111KB, 下载30次)

http://www.pudn.com/Download/item/id/1650133.html

[VHDL/FPGA/Verilog] Verilog

一些关于Verilog分频器设计.doc
Verilog divider design. Doc (2011-05-25, WORD, 9KB, 下载4次)

http://www.pudn.com/Download/item/id/1547161.html

[VHDL/FPGA/Verilog] SRAM--SDRAM--FLASH

SRAM和SDRAM的区别，存储器之间的区别
The difference between SRAM and SDRAM, pay attention to the difference between them (2011-03-03, WORD, 4KB, 下载1次)

http://www.pudn.com/Download/item/id/1443484.html

[VHDL/FPGA/Verilog] 5

基于SYSTEMVIEW的HDB3码编码器实验设计，看看吧
Based on the HDB3 Encoder SYSTEMVIEW experimental design and see for yourself (2010-11-09, WORD, 206KB, 下载3次)

http://www.pudn.com/Download/item/id/1340785.html

[VHDL/FPGA/Verilog] 8

利用verilog HDL编程驱动七段译码显示器，显示一位8进制变化。
Using verilog HDL programming seven segment decoder display driver, display an 8-ary change. (2010-10-12, WORD, 3KB, 下载4次)

http://www.pudn.com/Download/item/id/1315919.html

[VHDL/FPGA/Verilog] SDRAM

基于SDRAM的存储器接口设计，采用verilog编写
SDRAM memory interface design based on (2010-07-13, WORD, 978KB, 下载1次)

http://www.pudn.com/Download/item/id/1240683.html

[VHDL/FPGA/Verilog] EDA

用EDA实现串行输入并行输出的移位寄存器，附带仿真
Serial Input with EDA parallel output shift register, with simulation (2010-05-06, WORD, 4KB, 下载4次)

http://www.pudn.com/Download/item/id/1159484.html

[VHDL/FPGA/Verilog] adder

实验一 1位全加器的设计详细的试验步骤一节过程分析！
Experiment-1 adder design a detailed process analysis of test steps! (2010-04-23, WORD, 827KB, 下载3次)

http://www.pudn.com/Download/item/id/1140412.html

[VHDL/FPGA/Verilog] 2007

本数字示波器以单片机和FPGA为核心，对采样方式的选择和等效采样技术的实现进行了重点设计，使作品不仅具有实时采样方式，而且采用随机等效采样技术实现了利用实时采样速率为1MHz的ADC进行最大200MHz的等效采样。
The digital oscilloscope and a single-chip FPGA as the core, the choice of the sampling methods and the equivalent sampling technique designed to achieve a focus, so that not only works with real-time sampling, and the random sampling technique to achieve the equivalent of using real-time sampling rate the ADC for the 1MHz maximum equivalent 200MHz sampling. (2009-08-08, WORD, 14KB, 下载183次)

http://www.pudn.com/Download/item/id/871269.html

[VHDL/FPGA/Verilog] Nios_II_SOPC

基于Nios＿II软核处理器的通信信号源SOPC设计，很有用的资料．
Nios_II soft-core processor-based communication signal source SOPC design, very useful information. (2009-04-01, WORD, 330KB, 下载3次)

http://www.pudn.com/Download/item/id/696504.html

[VHDL/FPGA/Verilog] Verilog_FIFO_ram

一个可以综合的Verilog 写的FIFO存储器，word格式
An integrated Verilog wrote FIFO memory, word format (2008-03-17, WORD, 19KB, 下载53次)

http://www.pudn.com/Download/item/id/417546.html

[VHDL/FPGA/Verilog] FPGAprogram5

数控振荡器的频率控制字寄存器、相位控制字寄存器、累加器和加法器可以用VHDL语言描述，集成在一个模块中，提供VHDL源程序供大家学习和讨论。
NC oscillator frequency control word register, phase control word register, and processing instruments used accumulator can be used VHDL description, in an integrated modules provide VHDL source code for all learning and discussion. (2006-04-11, WORD, 3KB, 下载106次)

http://www.pudn.com/Download/item/id/169406.html

[VHDL/FPGA/Verilog] FPGAprogram4

16位计数器的设计，这里是实现上述功能的VHDL源程序，供大家学习和讨论。
16 counter design, here is the realization of the above-mentioned functional VHDL source code for all learning and discussion. (2006-04-11, WORD, 2KB, 下载35次)

http://www.pudn.com/Download/item/id/169398.html

[VHDL/FPGA/Verilog] FIR低通滤波器部分模块

一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。
This is a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2. (2005-05-09, WORD, 5KB, 下载205次)

http://www.pudn.com/Download/item/id/1115616821826897.html

[VHDL/FPGA/Verilog] 十字路口交通灯控制器设计

使用VHDL实现十字路口交通灯控制器设计，适用于初学者
use VHDL crossroads traffic signal controller design, applicable to beginners (2004-12-12, WORD, 29KB, 下载473次)

http://www.pudn.com/Download/item/id/1102856590942594.html

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