巴克码是通信传输实践中较为常用的编码技术，这个工程可以帮助初学者理解其原理
Barker code is a commonly used encoding technique in communication transmission practice, and this project can help beginners understand its principles (2023-09-22, VHDL, 31KB, 下载0次)
veriog设计锁存器、触发器、寄存器、移位寄存器等
Veriog designs latches, triggers, registers, shift registers, etc (2020-05-14, VHDL, 326KB, 下载0次)
同步状态机
由状态寄存器（触发器）作为状态记忆部件（常用正跳边沿触发的D触发器）
仅当触发信号到达时刻才可能发生状态改变
n个触发器最多有2n 个状态
Synchronized state machine
The state register (flip-flop) is used as the state memory unit (D flip-flop triggered by forward jump edge)
State changes may occur only when the trigger signal arrives
N flip-flops have at most 2n States (2018-12-14, VHDL, 223KB, 下载0次)
产生三角波 这是一个用VHDL在ISE平台上产生的三角波测试程序 用来检测AD路的输出的 各位看官来看看
Generate a triangle wave This is a triangle wave test program generated by VHDL on the ISE platform. It is used to detect the output of the AD road. (2018-06-05, VHDL, 309KB, 下载0次)
VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。
The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 priority encoder, 8 choose 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital frequency meter, digital clock, synchronous counter, sequence detector design. Sequence signal generator, general state machine etc.. (2018-02-26, VHDL, 40KB, 下载3次)
能够绘制数字电路的时序图，是fpga工程师时序设计和分析的神器
for digital circuit timming design and analysis (2017-12-27, VHDL, 235KB, 下载2次)
首先利用IP核记录sin和con波形，然后进行FSK调制，信息为数字信息
Firstly, the IP kernel is used to record the sin and con waveforms, and then the FSK is modulated, and the information is digital information (2017-10-12, VHDL, 4695KB, 下载1次)
产生m序列，2016年天津市赛区，11年眼图，核心代码
M sequence, 2016 Tianjin city division, 11 years of the eye, the core code (2017-07-24, VHDL, 2882KB, 下载1次)
100进制计数器的设计100进制计数器的设计
100 binary counter design (2010-01-07, VHDL, 1KB, 下载12次)
电视机彩条发生器，有文字，图案等多种选择模式
TV Color Bar Generator, with text, patterns and other selection mode (2009-12-19, VHDL, 7KB, 下载40次)
100分频的ISE综合仿真源程序，以及仿真波形
100division (2009-12-06, VHDL, 261KB, 下载7次)
verilog 中RLS算法的实现功能 已经在仿真窗口的波形实现
verilog about rls algorithm
(2009-11-10, VHDL, 1KB, 下载31次)
实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出.
Achieve the four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency and amplitude controlled output. (2009-08-29, VHDL, 10KB, 下载6次)
一个梁祝的音乐发生器
本压缩包是一个ppt
包含其原理及vhdl代码
经过本人验证过的
A music generator of the Butterfly Lovers package contains a ppt its principle and vhdl code after I verified (2009-07-02, VHDL, 317KB, 下载4次)
产生波形文件中需要注意的事项，很不错的呦，好不容易下到的
Waveform files generated needs attention, very good Yo, finally down to the (2008-12-19, VHDL, 390KB, 下载4次)
设计一个液晶显示驱动电路，要求能够显示至少两个周期的三角波形，并显示“T=30ms”的字样。
The design of a liquid crystal display driver circuit, the requirements are able to show that at least two cycles of the triangular waveform, and display T = 30ms message. (2008-12-18, VHDL, 1KB, 下载12次)
能够实现4中不同的波形，频率是可以控制的
Able to achieve 4 different waveforms, frequencies can be controlled (2008-12-13, VHDL, 10KB, 下载2次)
大唐公司的内部学习教程，很好的介绍了可编程器件的学习经验
Datang company s internal learning curricula, introduced a very good learning experience programmable devices (2008-12-02, VHDL, 944KB, 下载27次)
这是一个正弦信号发生器，其原理是利用mif文件产生正弦信号所需的幅值。
This is a sinusoidal signal generator, the principle is the use of mif documents required to have a sinusoidal signal amplitude. (2008-06-07, VHDL, 25KB, 下载3次)
FPGA工程文件 通过FPGA在LCD上显示“this is my frist program"的字体 已经验证，供大家学习使用。
FPGA through the FPGA project file in the LCD display (2008-05-19, VHDL, 616KB, 下载136次)