RISC V CNN加速器
RISC V CNN Accelerator (2024-03-03, Verilog, 0KB, 下载0次)
流水线RISC V处理器
Pipelined RISC V Processor (2024-02-16, Verilog, 0KB, 下载0次)
使用cocotb.对32位嵌入式RISC微处理器的Flash、UART和SDRAM控制器进行设计验证。，
Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb., (2023-10-15, Verilog, 0KB, 下载0次)
双核微控制器1.0版，
Dual-core Microcontroller ver1.0, (2023-09-20, Verilog, 0KB, 下载0次)
基于指令集设计了处理器的微体系结构。处理器应该实现ins...
The microarchitecture of a processor is designed based on an Instruction Set. Your processor should implement the instructions add, sub, and, or, mov, loadi, j and beq. All instructions are of 32-bit fixed length (2020-12-15, Verilog, 3158KB, 下载0次)
mARC处理器（mini-ARC，发音为marcee）是一个16位RISC处理器，实现了ARC进程的ISA...
The mARC processor (mini ARC, pronounced as marcee) is a 16-bit RISC processor implementing the ISA of the ARC processor. It is used in UEA 1121025 (Computer Architecture) to explain the microarchitecture of a very simple general- purpose microprocessor. It is written in Verilog. (2018-01-21, Verilog, 500KB, 下载0次)
RISC-V-单循环微处理器，，
RISC-V-Single-Cycle-Microprocessor,, (2020-10-29, Verilog, 9940KB, 下载0次)
Verilog管道RICSv处理器
Verilog Pipeline RICSv Processor (2022-05-23, Verilog, 312KB, 下载0次)
verilog中的RISC处理器
A RISC processor in verilog (2020-12-16, Verilog, 208KB, 下载0次)
RISC-V处理器
RISC-V processor (2022-07-15, Verilog, 26KB, 下载0次)
旋风分离器10 RISC-V FuseSoC芯
Cyclone 10 RISC-V FuseSoC core (2020-12-10, Verilog, 108KB, 下载0次)
实现了一个4级流水线无序RISC-V处理器，该处理器使用带预留站的tomasulo算法...
Implemented a 4 staged pipelined out of order RISC-V processor which uses tomasulo algorithm with reservation stations and reorder buffers. This was a course assignment in Processor Architecture course. (2021-05-03, Verilog, 11KB, 下载0次)
该处理器采用具有独立指令和数据存储器的HDL Verilog设计。显著特征...
The proposed processor is designed using HDL Verilog having separate instruction and data memory. The salient feature of proposed processor is pipelining, used for improving performance, such that on every clock cycle one instruction will be executed. Another important feature is that instruction set contains 14 instructions, which is very (2018-08-20, Verilog, 4KB, 下载0次)
32位-RISC-V-Full处理器设计，，
32-bits-RISC-V-Full-processor-design,, (2023-01-30, Verilog, 293KB, 下载0次)
Oscar RISC-V无序处理器
Oscar RISC-V Out Of Order Processor (2021-03-25, Verilog, 11KB, 下载0次)
基于RISC V的简单处理器
RISC V based Simple Processor (2022-02-22, Verilog, 245KB, 下载0次)
流水线RISC_V处理器
Pipelined RISC_V Processor (2020-06-05, Verilog, 14KB, 下载0次)
简易 risc-v 处理器设计
Design of simple risc-v processor (2020-03-12, Verilog, 4554KB, 下载0次)
具有一些非常简单的存储器和外围设备的picorv32 RISC-V处理器。对于Terasic DE-0 Nano
A picorv32 RISC-V processor with some very simple memory and peripherals. For Terasic DE-0 Nano (2019-04-15, Verilog, 158KB, 下载0次)
轻量级RISC-VRV32IMC微控制器内核。
Light-weight RISC-V RV32IMC microcontroller core. (2017-03-04, Verilog, 16KB, 下载0次)