教育负载存储指令集体系结构处理器模拟器
Educational load store instruction set architecture processor simulator (2013-03-20, Verilog, 0KB, 下载0次)
一种用于SIEVE的实验性Tiny86解码器和验证器，
An experimental Tiny86 decoder and verifier for SIEVE, (2023-10-19, Verilog, 0KB, 下载0次)
一个LED显示的简单计数器，通过一个转码器连接LEDA simple counter with LED display
A simple counter with LED display (2021-04-20, Verilog, 2890KB, 下载0次)
有一个复位键，循环蜂鸣器播放音乐，天空之城
Buzzer music playing,beep,sky (2020-07-09, Verilog, 5340KB, 下载0次)
将运算器模块与存储器模块进行连接.....................
Connect the arithmetic module with the memory module; (2020-06-29, Verilog, 210KB, 下载0次)
给予FPGA的can总线编程，FPGA实现CAN总线控制器源码
this software base on fpga Verilog,relizes the can bus communication. (2020-04-13, Verilog, 858KB, 下载9次)
基于FIR设计的100阶数字滤波器，选择的矩形窗
100 - order digital filter based on FIR (2020-03-06, Verilog, 11KB, 下载1次)
触发器的代码及测试文件，八选一数据选择器的代码及测试文件，全加器的代码及测试文件
Trigger code and test file, one out of eight data selector code and test file, full adder code and test file (2019-12-12, Verilog, 1KB, 下载0次)
单总线接口master控制器，可综合可编译
onewire interface controller (2019-11-29, Verilog, 252KB, 下载0次)
用四個器段顯示器來完成0到9999的上數計數器
Using four segment displays to complete the up counter from 0 to 9999 (2019-11-08, Verilog, 3496KB, 下载0次)
提出了PLL中小数分频器实现的方法和建议，值得参考
the N-divider of PLL (2019-06-02, Verilog, 2330KB, 下载5次)
用外部信号可以实现计数器进制数的控制代码
External signal can be used to achieve counter base control. (2018-11-23, Verilog, 4077KB, 下载0次)
uvm寄存器模型的示例和具体用法，包括仿真平台的使用
Examples and specific usage of UVM register model, including the use of simulation platform. (2018-10-21, Verilog, 81KB, 下载20次)
用于数字逻辑电路实验抢答器的设计，可以实现抢答器的基本功能
The design of the responder for digital logic circuits can realize the basic functions of responder. (2018-06-10, Verilog, 3114KB, 下载0次)
用Verilog语言编写程序实现8比特约翰逊计数器
Write a program in Verilog language to implement the 8 bit Johnson counter. (2018-04-11, Verilog, 10KB, 下载4次)
基于basys2的模60计数器设计，语言verilog
Design of module 60 counter based on basys2, Language Verilog (2017-11-30, Verilog, 10KB, 下载4次)
读写控制器，带满和空指示，拿出来和大家分享
Read-write controller (2017-11-14, Verilog, 3228KB, 下载1次)
用verilog语言实现数字电路低通滤波器
Implementation of digital circuit low-pass filter using Verilog language (2017-10-11, Verilog, 39KB, 下载24次)
实现线性寄存器的移位和反馈，通过FPGA开发板实现功能
The shift and feedback of the linear register are realized (2017-09-29, Verilog, 250KB, 下载3次)
控制蜂鸣器让它有规律的发出声音，使得蜂鸣器发出 SOS 紧急救难信号
Control buzzer so that it regularly sounds, making the buzzer SOS emergency rescue signal (2017-07-18, Verilog, 152KB, 下载2次)