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[VHDL/FPGA/Verilog] FPGADTMF

基于fpga的DTMF信号检测器的原理文档,可供开发参考
DTMF signal detector based on the principles of the document fpga, for development of reference (2016-06-22, WORD, 12KB, 下载7次)

http://www.pudn.com/Download/item/id/1466560876996303.html

[VHDL/FPGA/Verilog] Hardware-multiplier

基于VHDL的硬件乘加器设计,包括QUARTERS 的文件以及实验报告,便于参考和修改
Hardware multiplier design based on VHDL, including the QUARTERS file as well as the experimental report, ease of reference and modification (2015-12-20, WORD, 943KB, 下载1次)

http://www.pudn.com/Download/item/id/1450598522629663.html

[VHDL/FPGA/Verilog] RTL8305SC_EEPROM

RTL8305内部寄存器及EPROM映射详细介绍中文版,本人自己翻译的。
RTL8305 internal registers mapped in detail and EPROM Chinese version, I own translation. (2014-12-07, WORD, 24KB, 下载46次)

http://www.pudn.com/Download/item/id/2669303.html

[VHDL/FPGA/Verilog] report-of-calculator

基于DE2开发板的计算器设计文档报告,包括设计原理思路、设计硬件实现和设计结果展望
alculator design document report based on the DE2 development board, including the principle of design thinking, design the hardware implementation and the design results (2014-08-20, WORD, 364KB, 下载1次)

http://www.pudn.com/Download/item/id/2607247.html

[VHDL/FPGA/Verilog] LC

本系统是以FPGA(EP2C8Q240C8)为控制核心,由压控振荡器、PLL倍频器、高频功率放大器、遥控器及LCD显示模块组成的压控LC振荡器。能实现输出正弦波频率在15MHZ~35MHZ步进可调,其最小步进为5002HZ,频率稳定度为10-5。当输出信号的频率为30MHZ、峰峰值稳定在1V左右时,在+12V单电源工作的情况下,功率放大器能实现在50Ω纯阻性和50Ω+20pf容性负载上输出功率大于20mw。LCD显示模块能实时显示输出信号的峰峰值和频率,精度由于10 。
This system is based on FPGA ( EP2C8Q240C8 ) as the control core, by a voltage controlled oscillator, PLL multiplier, high frequency power amplifier, remote control and LCD display module comprising a voltage-controlled LC oscillator. Can realize the output sine wave frequency in the step 15MHZ~35MHZ is adjustable, the smallest Bu Jin 5002HZ, frequency stability 10-5. When the frequency of the output signal is 30MHZ, peak stable at about 1V, in+12V single supply situation, the power amplifier can be realized in 50 Ωto 50 Ω+20pf pure resistive and capacitive load on the output power is greater than 20mw. LCD display module can display the output signal and the peak frequency, precision due to 10 . (2012-07-30, WORD, 287KB, 下载17次)

http://www.pudn.com/Download/item/id/1952836.html

[VHDL/FPGA/Verilog] Temperature-Alarm

基于I2C的温度警报。每一秒扫描采样温度值,当温度超过设定值,蜂鸣器响。
I2C-based temperature alarm. Every second scan sampling temperature, when the temperature exceeds the set value, the buzzer rang. (2012-06-24, WORD, 3KB, 下载2次)

http://www.pudn.com/Download/item/id/1921581.html

[VHDL/FPGA/Verilog] Ji-jia-qi

用 verilog实现的基于FPGA的出租车计价器,只有源代码,没有相关说明
The source is Taximeter which is complishment by language verilog on FGPA, some college students whose major is computer science may be related to it (2012-01-05, WORD, 14KB, 下载9次)

http://www.pudn.com/Download/item/id/1751140.html

[VHDL/FPGA/Verilog] Chebyshev-filter

主要介绍切比雪夫滤波器参数的计算,其主要特点是误差值在规定频段上等波纹变化
Introduces Chebyshev filter parameter calculation, the main feature is the error value in the upper band ripple requirement changes (2011-08-06, WORD, 30KB, 下载9次)

http://www.pudn.com/Download/item/id/1615887.html

[VHDL/FPGA/Verilog] music

完成一个简易的音乐播放器,可以完成上一曲,下一曲,顺序播放,停止,暂停和液晶显示,同时还增加了单曲循环播放功能。在理论分析的基础上,用VHDL语言编写源代码,再配合具体电路连接,实现对蜂鸣器振动的控制,以及对各项显示功能的切换控制等。
Complete a simple music player that can be completed on a next one, the order of play, stop, pause, and liquid crystal display, but also increased the single loop playback. In the theoretical analysis, based on the use of VHDL language source code, together with the specific circuit connections, to achieve the buzzer vibration control, and the display switching control. (2011-06-29, WORD, 149KB, 下载12次)

http://www.pudn.com/Download/item/id/1584823.html

[VHDL/FPGA/Verilog] Hardware_development_VHDL8_bit_asynchronous_counte

硬件开发VHDL8位异步计数器一个课程设计Hardware development VHDL8 bit asynchronous counter
Hardware development VHDL8 bit asynchronous counter of a course design Hardware development VHDL8 bit asynchronous counter (2010-08-01, WORD, 157KB, 下载3次)

http://www.pudn.com/Download/item/id/1256550.html

[VHDL/FPGA/Verilog] jiaotongdeng

这是用FPGA实现的交通灯控制器,其中有完整的程序源码及其电路图,自己用过的,希望有些帮助
This is the light controller with FPGA realizing, including a complete program source and its circuit, by oneself, hope some help (2009-05-19, WORD, 36KB, 下载14次)

http://www.pudn.com/Download/item/id/767522.html

[VHDL/FPGA/Verilog] 1

基于eda中vhdl语言的一位全加器的设计,详细的设计过程和实验现象,相互学习
Based on EDA VHDL language in a full adder design, detailed design process and the experimental phenomena and learn from each other (2008-11-20, WORD, 839KB, 下载4次)

http://www.pudn.com/Download/item/id/584180.html

[VHDL/FPGA/Verilog] jishuqi

本文十一个计数器的实验报告,阐述了设计的思路,设计的具体方案,以及上机操作的步骤,描述非常详细!
This article counters 11 Experimental report on the design ideas, design specific programs, as well as steps on the machine, described in great detail! (2008-11-02, WORD, 119KB, 下载8次)

http://www.pudn.com/Download/item/id/571350.html

[VHDL/FPGA/Verilog] pinlvji

这是一个基于FPGA的频率计和相位计的设计方案
This is an FPGA-based Cymometer and design phase of the program (2007-07-03, WORD, 660KB, 下载65次)

http://www.pudn.com/Download/item/id/302761.html

[VHDL/FPGA/Verilog] xuhuanjiucuo

循环纠错码译码器VHDL代码。通信方面FPGA设计基础代码。
cycle error correction decoder VHDL code. Communications FPGA design code base. (2007-04-14, WORD, 3KB, 下载21次)

http://www.pudn.com/Download/item/id/268028.html

[VHDL/FPGA/Verilog] vhdl2DPSK

用VHDL设计了一种2DPSK信号产生器,测试和实际应用表明其性能稳定可靠。
VHDL design of a 2DPSK Signal Generator, testing and practical application show that its performance is stable and reliable. (2007-01-14, WORD, 321KB, 下载30次)

http://www.pudn.com/Download/item/id/242208.html

[VHDL/FPGA/Verilog] 16BITCOUNTER

自己作课题用到的16位计数器,已经过仿真试验,具有较好的计数准确性。
their subjects used for the 16 counters, has been through the simulation tests, has better accuracy of the counting. (2006-12-26, WORD, 2KB, 下载3次)

http://www.pudn.com/Download/item/id/236702.html

[VHDL/FPGA/Verilog] numberword

计数器控制程序,希望能够给大家帮助!文件在MAX PLUS下开发,调试通过
counter control procedures, we hope to be able to help! MAX PLUS document under development, through debugging (2006-06-28, WORD, 1KB, 下载3次)

http://www.pudn.com/Download/item/id/198991.html

[VHDL/FPGA/Verilog] s_pandp_s

用VHDL编写的并串转换和串并转换实例,希望对您有所帮助,其中输入数据是时钟的16倍
prepared using VHDL and string conversion and string conversion and examples, and I hope to help you, the input data which is 16 times the clock (2006-05-21, WORD, 2KB, 下载357次)

http://www.pudn.com/Download/item/id/186654.html

[VHDL/FPGA/Verilog] sl.v

路灯控制器 采用了状态机的概念编程,其中采用了信号检测进程防止干扰信号驱动芯片工作
lights controller state machine used the concept of programming, where the signal detection processes to prevent signal interference driver chips work (2006-03-27, WORD, 1KB, 下载38次)

http://www.pudn.com/Download/item/id/160916.html
总计:90