[处理器开发] RISC-V-unicycle
VHDL中RISC-V单循环处理器实现的存储库和UnB计算机组织和架构课程材料（2023 2）
Repository for RISC-V Unicycle Processor Implementation in VHDL and Course Material for Organization and Architecture of Computers at UnB (2023 2) (2024-01-26, VHDL, 0KB, 下载0次)
[处理器开发] ControllerVGA_MicroSD
VHDL项目。实现FSM，用于使用Digilent Nexys 4从microSD卡读取图像并在VGA显示器上显示它们...，
VHDL project. Implementation of a FSM for reading images from a microSD card and displaying them on a VGA monitor using Digilent Nexys 4 DDR board (2023-08-31, VHDL, 0KB, 下载0次)
[处理器开发] T03x
作为至少三个线程交错的多线程微处理器，其针对针兼容Paulino riscy内核，
A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores, (2023-03-07, VHDL, 0KB, 下载0次)
[处理器开发] T02x
作为至少两个线程交错的多线程微处理器，其针对针兼容Paulino riscy内核，
A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores, (2023-03-07, VHDL, 0KB, 下载0次)
[处理器开发] T13x
T0x多线程内核的扩展版本，具有定制的通用参数化SIMD MIMD向量协处理器和支持...，
An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP (2023-03-08, VHDL, 0KB, 下载0次)
[处理器开发] pcycle
我的第一个用HDL语言编写的处理器
My first processor written in HDL language (2022-08-21, VHDL, 192KB, 下载0次)
[处理器开发] RISC-V-Single-Cycle-Processor
基于RV32I基本指令集的RISC-V单周期处理器的设计与实现。...的建模...
Design and implementation of a RISC-V Single-Cycle processor based on the RV32I base instruction set. Modeling of the RV32I building blocks was done using VHDL. RISC-V assembly and code generation tools were used to load a set of 32-bit RISC-V instructions into instruction memory and execute these instructions on the processor. (2021-10-11, VHDL, 18KB, 下载0次)
[处理器开发] riscV-processor
这是一种基于RISC指令集架构的简单处理器设计。使用Xilinx Vivado实现它。
This is simple processor design, based on the RISC instruction set architecture. Used Xilinx Vivado to implement it. (2022-10-04, VHDL, 11987KB, 下载0次)
[处理器开发] CEP
概念非处理器RISC-V et实现描述指令和系列指令类型（VHDL&A...
Conception d un processeur RISC-V et implémentation de ses instructions et familles d instructions typiques (VHDL & Assembleur RISC-V). (2021-10-07, VHDL, 1027KB, 下载0次)
[处理器开发] 16-bit-RISC-Processor-VHDL
本课题用VHDL语言设计了一个16位Risc处理器，并在Modelsim中进行了仿真和测试。
This project design a 16 bit Risc Processor with VHDL and simulate it and test it in Modelsim. (2020-06-10, VHDL, 408KB, 下载0次)
[处理器开发] arilla
Arilla-一个基于RISC-V的微型计算机系统，具有PS2鼠标控制器和12位RGB SVGA图形卡，正在运行...
Arilla - a RISC-V based microcomputer system, with a PS2 mouse controller and 12-bit RGB SVGA graphics card, running Arilla Paint. (2021-09-07, VHDL, 869KB, 下载0次)
[处理器开发] IoT_Platform_for_BlockchainApplications
使用Arm CM3、Arty S7-50板和Pmod ESP32连接到互联网的微控制器。本项目计划...
A micro controller with connection to the Internet using Arm CM3, the Arty S7-50 board and Pmod ESP32. This project provides Blockchain support with Key Generation and Signature Generation/Validation over the Bitcoin Curve. (2022-09-25, VHDL, 273586KB, 下载0次)
[处理器开发] STM32启动代码
利用GPIO口模拟I2C通信，驱动富士通MB85RC系列铁电存储器 ** 支持的型号：MB85RC64/64V,MB85RC128/128V,不支持MB85RC16/16V
The master inputs the device address word (8 bits) following the start condition, and then the slave outputs (2019-07-05, VHDL, 131KB, 下载3次)
[处理器开发] DLX_verilog-kuangjia
这是我们学校上课所使用的微处理器体系结构课程实验的代码框架，可以在此基础上添加新的指令，DLX指令集
This is our school curriculum experiments microprocessor architecture code framework, can add a new instruction on this basis, the DLX instruction set (2012-12-05, VHDL, 26KB, 下载6次)
[处理器开发] CISC
cisc8位微处理器的vhdl源码。处理功能：求出1到任意整数N之间的奇数之和。并输出。
cisc8 bit microprocessor vhdl source code. Processing functions: find an integer N between 1 and any odd sum. And output. (2011-11-27, VHDL, 866KB, 下载13次)
[处理器开发] CPU_reference
采用verilog语言描述的 arm7架构处理器。
使用quartusII+modelsim se 进行开发和验证
Using verilog language to describe the arm7-based processors. Use quartusII+ modelsim se for development and validation of (2009-08-26, VHDL, 160KB, 下载19次)
[处理器开发] AMBA.Spec.Rev2.0
amba2.0协议，是arm公司的一种通信协议，Java处理器可以通过其与产品进行通信
amba2.0 agreement, is an arm' s communication protocols, Java processor can communicate with the product (2009-08-02, VHDL, 868KB, 下载8次)
[处理器开发] risc
嵌入式risc处理器源码，包含设计文档，原理图，testbench，及外围接口，使用verilog实现。
Source embedded RISC processors, including design documents, schematics, testbench, and peripheral interfaces, the use of Verilog to achieve. (2008-12-08, VHDL, 126KB, 下载84次)
[处理器开发] ARMAndFPGAAppliingOnDataCommunicatin
ARM处理器和FPGA在数据传输中的应用与研究
ARM processor and FPGA data transmission in the Application and Research (2008-10-07, VHDL, 1961KB, 下载16次)
[处理器开发] rong
一个IIC总线的代码，一个VGA显示文字代码，目前VGA可以显示彩条，但是现实文字较少，一个本科学生兰编写，还不错，共享下，大家参考，IIC编写的比较经典，可以 学习怎么写一个处理器的外设控制器。
IIC bus is a code, a VGA display text code, the current color VGA displays, but less realistic characters, a lan to prepare undergraduate students, but also good to share, the U.S. reference, IIC comparison prepared classics, can learn how to write a processor peripheral controller. (2008-07-18, VHDL, 1732KB, 下载32次)