包括开发的HDL代码、波形图和ARM处理器实现的示意图。代码是根据......制定的...，
Includes developed HDL codes, pictures of waveforms and schematics for the implementation of an ARM processor. Codes were/are developed by moein maleki and ashkan jafari, for Architecture Lab, Fall of 2022. (2023-09-23, Verilog, 0KB, 下载0次)
基于Box-Mueller方法的FPGA加性高斯白噪声发生器
FPGA Additive White Gaussian Noise Generator Using the Box Mueller Method (2016-10-07, Verilog, 4537KB, 下载0次)
从涉及FPGA的架构中创建模拟正弦信号的项目。它是用一个DDS核心来生成...
Project which creates an analogic sine signal from an architecture that involves FPGA. It were used a DDS core to generate the sine and SPI communication to control DAC conversor (AD5791 Analog Devices). To choose the sine frequency and the update frequency of a new data we developed a cpp application. The "documentation" folder has more (2014-03-26, Verilog, 6581KB, 下载0次)
以FPGA为目标，用VHDL语言编写了一个具有环形振荡器结构的真随机数发生器。
A true random number generator with ring oscillators structure written in VHDL targeting FPGA s. (2020-09-22, Verilog, 12KB, 下载0次)
Verilog AMBA AHB多层互连发生器
A Verilog AMBA AHB Multilayer interconnect generator (2017-08-08, Verilog, 26KB, 下载0次)
此项目(完全自己编写)是基于FPGA的测频功能实现,拥有自设发生频率、测试频率、频率显示等完备功能
This project (written by myself) is the realization of frequency measurement function based on FPGA, with self setting frequency, test frequency, frequency display and other complete functions (2021-04-19, Verilog, 4946KB, 下载0次)
打包好的ISE工程，可以直接使用，通过ISE内部调用的IP核产生输出正弦信号。
The packaged ISE project, which can be used directly, generates output sinusoidal signals through the IP core invoked internally by ISE. (2020-07-31, Verilog, 13009KB, 下载2次)
可用FPGA实现DA输出，输出波形有三角波和正弦波形
The Da output can be realized by FPGA, and the output waveform includes triangle wave and sine wave (2020-06-27, Verilog, 178KB, 下载4次)
非常详细的串行输入代码，内有仿真的波形图，还有编写代码的状态图和思路讲解。
very detailed explanation (2020-03-04, Verilog, 87KB, 下载2次)
使用ROM存储正弦波MIF，由地址产生模块和频率控制模块，输出FSK信号
FPGAFSKsignalgennerater (2019-07-06, Verilog, 8804KB, 下载1次)
可以用来代替模拟PWM发生器，产生PWM的速度可达200M。
It can be used to replace the analog PWM generator. The speed of generating PWM can reach 200M. (2019-04-06, Verilog, 5KB, 下载2次)
可生成10位控制的PWM波形的verlog代码块。
The verlog code block of 10-bit PWM waveform can be generated. (2019-03-29, Verilog, 1KB, 下载0次)
数字示波器实验，利用AD、DA和VGA三个外设来实现简易示波器，DA外设发送正弦波给AD外设，AD外设解析成数字信号将数据送给VGA外设进行显示。在VGA上可以看到DA外设发送的波形、波形频率和波形峰峰值。
In the experiment of digital oscilloscope, AD, DA and VGA are used to realize simple oscilloscope. DA peripheral transmits sine wave to AD peripheral. AD peripheral resolves into digital signal and sends data to VGA peripheral for display. The waveform, waveform frequency and peak value of DA peripheral can be seen on VGA. (2019-03-13, Verilog, 3791KB, 下载6次)
利用AD、DA和VGA三个外设来实现简易示波器，DA外设发送正弦波给AD外设，AD外设解析成数字信号将数据送给VGA外设进行显示。在VGA上可以看到DA外设发送的波形、波形频率和波形峰峰值。
The simple oscilloscope is realized by using AD, DA and VGA peripherals. The DA peripheral sends sine wave to the AD peripheral, and the AD peripheral resolves into digital signal to send data to the VGA peripheral for display. On VGA, we can see the waveform, waveform frequency and waveform peak value transmitted by DA peripheral. (2018-10-16, Verilog, 3350KB, 下载4次)
system generatpr 的工程，实现用dds模块产生sine和cosine两路信号
The Engineering of system generator, using dds Module to generate sine and cosine signals (2018-09-10, Verilog, 27KB, 下载0次)
i2c(I2C)波形记录详解，帮助理解i2c时序，OV7670 的SCCB (I2C)波形记录.pdf
OV7670 SCCB (I2C).pdf (2018-06-04, Verilog, 276KB, 下载4次)
二选一多路选择器，含程序代码，含仿真波形图
Two select a multi path selector, including program code, including simulation waveform. (2018-05-17, Verilog, 109KB, 下载1次)
周期为15的M序列发生器，用quartus仿真成功。
M sequence generator with a period of 15 (2018-05-11, Verilog, 8KB, 下载3次)
在FPGA硬件平台上，生成一个IP核，调用IP核来形成信号发生单元
A sin generater based on IP core in FPGA (2018-05-07, Verilog, 51KB, 下载2次)
汽车VCU控制器测试工装的程序，STM32单片机扩展总线读写FPGA内部RAM，DDS方式产生PWM，PWM频率，脉宽测量功能
Automotive VCU controller test tooling procedures, STM32 microcontroller expansion bus read and write FPGA, the internal RAM, DDS way to generate PWM, PWM frequency, pulse width measurement function (2017-07-12, Verilog, 7495KB, 下载9次)