不需要os的jpeg編碼器
能夠嵌入在沒有os的fpga上或是在linux
It is an open source JPEG codec library, including both encoder and decoder.
Different to other implementations, it is designed for embedded system and is
aware of the need of embedded systems. Some advantages like
1. small memory footprint
2. easy to be ported to various processors and platforms
2. easy to run with or without embedded OS and support various embedded OS
3. easy to be ported to run with ESL tools, like Handel-C
4. easy to be ported to multi-processor systems
5. easy to can be implemented on FPGA. (2016-04-25, Unix_Linux, 159KB, 下载1次)
基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核,实现了基于FFT的音频信号分析
Altera Cyclone II FPGA family based embedded high-performance embedded IP core (Nios) soft core processor to achieve a FFT-based audio signal analysis (2015-03-04, Unix_Linux, 2KB, 下载11次)
本文件是针对OpenRISC软核处理器的嵌入式Linux系统的Device Tree文件。其中不仅描述了OpenRISC的基本部件，如CPU，ETHERNET，RAM等，还描述了一个来自opencores网站的I2C controller
For OpenRISC embedded platform Linux device tree file. In addition to the device tree contains the necessary components such as CPU, RAM, etc. opencores website also contains a source of an I2C controller (2013-11-19, Unix_Linux, 1KB, 下载2次)
提供1024位的连环AT24C01电可擦可编程
只读存储器(eepm)组织成128字的8位每个。该设备是
优化用于在许多工业和商业应用,低功率
和低电压操作是必要的。可以在空间的AT24C01储蓄
8针PDIP,8针MSOP,8针TSSOP,8针JEDEC小块集成电路包和是
可通过2线串行接口。此外,整个家庭可在5.0 v
(4.5 v至5.5 v),2.7 v(2.7 v至5.5 v),2.5 v(2.5 v至5.5 v)和1.8 v(1.8 v至5.5 v)版本-
的联系。
1024 provided a chain AT24C01 electrically erasable programmable read-only memory (eepm) organized into 128 words 8 each. The device is optimized for use in many industrial and commercial applications, low power and low voltage operation is necessary. AT24C01 savings in space, 8-pin PDIP, 8-pin MSOP, 8-pin TSSOP, 8-pin JEDEC soic package and is available through a 2-wire serial interface. In addition, the entire family is available in 5.0 v (4.5 v to 5.5 v), 2.7 v (2.7 v to 5.5 v), 2.5 v (2.5 v to 5.5 v) and 1.8 v (1.8 v to 5.5 v) version- linked. (2013-06-26, Unix_Linux, 160KB, 下载0次)
PCIE-DDR2-双通道ADDA板主要用于AD数据的记录与回放。该板主要使用Xilinx公司的Virtex5 FPGA，通过PCIE IP核与主机通讯，存储系统包括DDR2 SDRAM和FLASH，为各种软件无线电技术的应用提供了一个非常强大的单插槽收发器解决方案。
PCIE-DDR2 dual-channel ADDA board is mainly used for the AD data recording and playback. The board Virtex5 the FPGA using Xilinx PCIE IP core and the host communication, storage systems, including DDR2 SDRAM and FLASH, and provides a very powerful single slot transceiver solutions for a variety of software radio technology.
(2012-03-20, Unix_Linux, 249KB, 下载208次)
摘 要： 可编程片上系统设计是一个崭新的、富有生机的嵌入式系统设计技术研究方向。本文在阐述可编程逻辑器件特点及其发展趋势的基础上，探讨了智力产权复用理念、基于嵌入式处理器内核和xilinx FPGA的SOPC软硬件设计技术，引入了基于英特网可重构逻辑概念并提出了设计实现方法，为基于FPGA的嵌入式系统设计提供了广阔的思路。
Abstract: Programmable System on Chip design is a new and vibrant direction of embedded system design technology. This paper describes the development of programmable logic device characteristics and trends, based on the reuse of intellectual property rights concept, based on xilinx FPGA embedded processor core and the SOPC hardware and software design techniques, the introduction of Internet-based reconfigurable logic Design concept and implementation method is proposed for FPGA-based embedded system design provides a broad way of thinking. (2011-04-14, Unix_Linux, 65KB, 下载7次)
一个VHDL电梯控制器的程序
1、 每层电梯的入口处设有上下请求开关，电梯内设有乘客到达层次的停站请求开关。
2、 设有电梯所处位置指示装置及电梯运行模式（上升或下降）指示装置。
3、 电梯每秒升降一层。
4、 电梯到达有停站请求的楼层后，经过1s电梯打开，开门只是灯亮，开门4s后，电梯门关闭（关门指示灯灭），电梯继续运行，直至执行完请求信号后停在当前楼层。
5、 能记忆电梯内外的所以请求信号，并按照电梯运行规则依次响应，每个请求信号保留至执行后消除。
6、 电梯运行规则：当电梯处于上升模式时，只响应比电梯所在位置高的上楼信号，由下至上依次执行，直到最后一个上楼请求执行完毕，如更高层有下楼请求时，则直接升到有下降请求的最高楼接客，然后进入下降模式，但电梯处于下降模式时，则与上升模式相反。
7、 电梯初始状态为一层门开。
err (2008-01-14, Unix_Linux, 122KB, 下载345次)
可编程器件大厂Xilinx提供的高速多状态编码8b_10b编码器，可直接使用在Xilinx公司器件的设计上
Xilinx programmable device manufacturers to provide high-speed multi-state coding 8b_10b encoder, direct access to the Xilinx devices on the design (2005-12-31, Unix_Linux, 175KB, 下载61次)
专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550 ，包含完整的使用说明手册、testbench、可综合，如果被网站认可，将继续上传其余的几个更好的core。
specialized processor and peripheral interfaces famous ipcore CAST product manufacturers UART H16 550, including full use manual testbench can be integrated, if the site is approved, the rest will continue to upload a few better core. (2005-12-31, Unix_Linux, 377KB, 下载88次)
用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助
I2C bus contrll functions implemented by Verilog HDL. (2005-09-15, Unix_Linux, 869KB, 下载210次)