pentru masurarea timpului电路；Afisarea valorii Numaratorelor pe 7 seg显示器；Adaugarea de操作码uri；Adaugarea unor模块存储器
Circuit pentru masurarea timpului; Afisarea valorii numaratoarelor pe 7 seg display; Adaugarea de opcode-uri; Adaugarea unor module de memorie (2024-04-05, Verilog, 0KB, 下载0次)
ECE 552流水线处理器
ECE 552 pipelined processor (2024-02-29, Verilog, 0KB, 下载0次)
基于FPGA的出租车计价器
Taxi meter based on FPGA (2024-02-20, Verilog, 0KB, 下载0次)
在线模糊控制器芯片
Online Fuzzy Controller Chisel (2024-01-18, Verilog, 0KB, 下载0次)
MESI一致性区间控制器
MESI Coherency InterSection Controller (2014-07-17, Verilog, 0KB, 下载0次)
基于UVM的apb定时器验证
apb-timer verification based on UVM (2023-11-06, Verilog, 0KB, 下载0次)
混合内存立方体控制器，
Hybrid Memory Cube Controller, (2023-07-20, Verilog, 0KB, 下载0次)
quartus 13.0的破解器鹅妈妈木木木木木木木木木木木木木木木木木木
The cracker of quartus 13.0 (2020-06-23, Verilog, 13KB, 下载0次)
设计一个串行数据检测器，当连续输入三个或更多1时输出1，否则输出0
Design a detector for serial data It outputs 1 when three or more 1 input continuously and outputs 0 otherwise (2020-01-02, Verilog, 30KB, 下载1次)
用兩個七段顯示器完成一個0到99的上數計數器
Using two seven segment displays to complete an up counter from 0 to 99 (2019-11-08, Verilog, 2750KB, 下载0次)
我目前只写了数据 通过I2C 没有去读出来看
7511和7513应该差不多啊
还有原理图是我自己设计的额 不确定是否正确
现在就是配置完后 HDMI接口上无任何输出 也测不到任何波形
I've only written data so far, but I haven't read it through I2C.
7511 and 7513 should be about the same.
And the schematic diagram is my own design of the amount of uncertainty is correct or not.
Now it's time to configure the HDMI interface without any output or waveform. (2019-07-09, Verilog, 72KB, 下载1次)
好用的SDRAM控制器，经过FPGA平台验证过。
It is a SDRAM controller with verilog code.
It is a good code, and confirmed. (2018-10-08, Verilog, 2757KB, 下载5次)
基于Verilog HDL语言开发的三层电梯控制器
Three tier elevator controller based on Verilog HDL language (2018-05-19, Verilog, 143KB, 下载15次)
基于VHDL实现的十六位流水线处理器包括控制器等模块
VHDL based sixteen bit pipelined processor, including controllers and other modules. (2018-05-13, Verilog, 373KB, 下载0次)
滤波器的实现，总共为4种，是简单的coif3滤波器的实现方法
The implementation of the filter, a total of 4, is a simple coif3 filter implementation method (2018-03-24, Verilog, 4KB, 下载3次)
一款运动计时器的设计，包含了时、分、秒的设计。
The design of a sports timer includes hour, minute and second designs. (2018-03-21, Verilog, 12KB, 下载1次)
器件EP4CE6F22C8N 一位半加器
Device EP4CE6F22C8N a half adder (2018-01-16, Verilog, 2889KB, 下载1次)
实现了264解码器的解码功能，能在modelsim上仿真通过
The decoding function of the 264 decoder is realized, which can be simulated on the Modelsim. (2017-12-28, Verilog, 944KB, 下载3次)
MT9P031摄像头驱动配置寄存器，给出了CMOS驱动基本配置中必须要配置的寄存器，和相关初始值
camera driver configuration register of MT9P031 (2017-07-11, Verilog, 1KB, 下载3次)
用verilog实现数字滤波器的功能,基于quatursii平台。内含源代码
With Verilog digital filter function, based on the quatursii platform. Contain source code (2017-07-06, Verilog, 3991KB, 下载1次)