DASS HLS编译器，
DASS HLS Compiler, (2023-10-04, VHDL, 0KB, 下载0次)
硝基部件的图像传感器接口控制器和仿真模型，
Image sensor interface controller and simulation model for nitro parts, (2023-09-07, VHDL, 0KB, 下载0次)
fir滤波器顶层模板
用于构建下层代码的基础，选用calculator 和shift_register模块
fir filter top license (2020-07-31, VHDL, 1KB, 下载0次)
半加器的代码，以及ucf文件，仿真已过，可在basys2上运行
The code of the semi adder, as well as the UCF file, has passed the simulation and can be run on basys2 (2020-05-03, VHDL, 933KB, 下载0次)
用VHDL语言实现数据选择器，包含源码和pof文件。
Using VHDL language to realize data selector, including source code and POF file. (2020-04-05, VHDL, 17KB, 下载0次)
quartusII 9.1，位同步提取电路，可以实现位同步时钟提取，其中包括分频器，和由D触发器以及与门组成的鉴相器模块。
Quartus II 9.1, bit synchronous extraction circuit, can realize bit synchronous clock extraction, including frequency divider, phase discriminator module composed of D trigger and and gate. (2020-01-11, VHDL, 7KB, 下载2次)
VHD32X32乘法计算器, 支持16位的32*32VHDL 乘法计算器，带TEST bench
VHDL 32X32 matrix multiplex calculator (2019-04-30, VHDL, 7749KB, 下载0次)
基于FPGA的ddr3 sdram控制器的设计资料
Design Data of DDR3 SDRAM Controller Based on FPGA (2019-01-14, VHDL, 1310KB, 下载0次)
数字与逻辑设计电路实验设计：实现4位扭环计数器。
4 bit torsion ring counter (2018-11-30, VHDL, 3KB, 下载0次)
使用vhdl语言原件例化设计数字频率计，并用6位7段数码管计数。模块包括：十进制计数器，6位10进制计数器，Reg24 锁存器、Fp 分频器、Ctrl 频率控制器、Disp 动态显示。
The digital frequency meter is designed by using VHDL language as an example and counted by 6-bit 7-segment digital tube. Modules include: decimal counter, 6-bit decimal counter, Reg24 latch, Fp frequency divider, Ctrl frequency controller, Disp dynamic display. (2018-11-30, VHDL, 11KB, 下载1次)
2、熟悉常用电子产品测试仪器设备；
2.熟悉基本数字电路，模拟电路理论，具有EMC方面的知识，动手能力强；
3、具备模电/数电基础理论知识及电路分析处理能力，会使用硬件设计工具 精通模拟、数字电路，熟悉信号采集与控制及各种数字电路接口，具备独立的硬件设计调试能力；
4、会使用示波器、万用表、信号发生器等常用测试仪器操作；
5.熟练使用C语言书写底层程序。
5、熟悉C语言和电路原理图，能够编写单片机外围电路驱动代码；
6、熟悉Altium Designer或Cadence、KEIL等常用IDE，熟悉M3、M4常用芯片；
3.熟练应用软件绘制原理图、PCB板图；
5、懂如UART、232、485、I2C、SPI、CAN、LINE、USB等。
2, familiar with commonly used electronic products testing instruments and equipment;
2. Familiar with basic digital circuit and analog circuit theory, with EMC knowledge and strong hands-on ability;
3. Have basic theoretical knowledge of analog / digital electricity and circuit analysis and processing ability, be proficient in analog and digital circuits using hardware design tools, be familiar with signal acquisition and control and various digital circuit interfaces, and have independent hardware design and debugging ability.
4, will use oscilloscope, multimeter, signal generator and other commonly used test instruments;
5. Proficient in using C language to wr (2018-11-06, VHDL, 2772KB, 下载1次)
基于vhdl的八位全加器设计及仿真 包含半加器，一位全加器等基本单元
The design and Simulation of the eight bit full adder based on VHDL include half adder, full adder and other basic units (2018-09-05, VHDL, 3025KB, 下载0次)
基于FPGA的16QAM调制器设计与实现
Design and implementation of 16QAM modulator based on FPGA (2018-06-14, VHDL, 2024KB, 下载4次)
实现频率综合器AD4350配置！产生单点。需要产生其他点，改变寄存器值就行了。
Implement AD4350 configuration! (2018-01-12, VHDL, 73KB, 下载2次)
通过调用一位全加器模块,实现四位全加器功能
By calling a full adder module, four full adder function (2012-12-29, VHDL, 1KB, 下载2次)
计算机组成原理实验通用寄存器组。仅供大家参考。
Computer Organization experimental general-purpose register group. Only for your reference. (2009-12-15, VHDL, 278KB, 下载75次)
七人表决器。有七个输入口，以多数胜于少数的结果进行表决
Seven voting machine. There are seven input to the majority of the results is better than a small number of voting (2009-08-05, VHDL, 99KB, 下载10次)
使用函数实现简单的八位处理器
软件开发环境：ISE 7.1i
仿真环境：ISE Simulator
1. 这个实例实现通过ISE Simulator工具实现一个可以进行两个八位操作数四种操作的简单处理器；
2. 工程在project文件夹中，双击mpc.ise文件打开工程；
3. 源文件在rtl文件夹中，mpc.v为设计文件，mpc_tb.tbw是仿真波形文件；
4. 打开工程后，在工程浏览器中选择mpc_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，进行行为仿真，即可得到仿真结果。
The use of a simple function to achieve the eight-processor software development environment: ISE 7.1i simulation environment: ISE Simulator 1. This example through the ISE Simulator tool to achieve the realization of a two operand four of eight simple processor operation 2. works in the project folder, double-click to open the project file mpc.ise 3. rtl source file in the folder, mpc.v documents for the design, mpc_tb.tbw is the simulation waveform files 4. to open a project, a browser in the works Select device mpc_tb.tbw, double-click in the Process View in the " Simulation Behavioral Model" option, to carry out acts of simulation, simulation results can be obtained. (2009-04-09, VHDL, 216KB, 下载8次)
电子琴，quartus开发环境，硬件连接模型，蜂鸣器
piano (2009-03-27, VHDL, 1523KB, 下载10次)
变频器移相控制，有死区生成,短路保护等功能
Phase-shifted inverter control, dead zone has generated, short-circuit protection functions (2008-05-16, VHDL, 182KB, 下载48次)