设计要求层次设计。底层的设计实体有 3 个:16 位寄存器,具有复位功能和 允许写功能;一个 2-4 译码器,对应寄存器写操作;一个 4 选 1 多路开关,负责 选择寄存器的读出。顶层设计构成一个完整的通用寄存器。
The design requires hierarchical design. There are three design entities in the bottom layer: 16 bit register with reset function and write allowed function; a 2-4 decoder, corresponding to register write operation; a 4-by-1 multi-channel switch, responsible for selecting register read-out. The top-level design constitutes a complete general register. (2020-06-18, VHDL, 131KB, 下载0次)
用VHDL语言实现三八译码器,包含源码和pof文件。
Using VHDL language to realize 38 decoder, including source code and POF file. (2020-04-05, VHDL, 18KB, 下载2次)
这是一个半加器的编码,功能简单,编程简单
This is a half adder code, simple in function and programming (2020-03-19, VHDL, 1483KB, 下载0次)
基于VHDL的多路抢答器,用LCD12864进行显示
Multiplex answering device based on VHDL is displayed with LCD12864 (2019-06-17, VHDL, 701KB, 下载2次)
基于VHDL的篮球计时计分器设计
包括24秒倒计时,12分钟倒计时,休息时间,加时赛,计分
Design of Basketball Timing Scorer Based on VHDL (2019-04-24, VHDL, 3616KB, 下载1次)
任意转换数制,HDL必备,可以使你的方便解决数字逻辑的HDL问题
Arbitrary conversion number system (2018-11-17, VHDL, 9KB, 下载0次)
用vhdl语言实现优先编码器,数字逻辑基础
Using VHDL language to realize priority encoder, digital logic foundation (2018-11-03, VHDL, 2920KB, 下载0次)
9999进制计数器,可进行0~9999数字计数
9999 binary counter, which can carry out 0~9999 digital counting. (2018-10-25, VHDL, 1435KB, 下载0次)
无软核调用,采用verilog语言编写CAN控制器代码,附验证
No soft core call, CAN controller code (2018-08-23, VHDL, 1679KB, 下载0次)
FPGA实现DDR3控制器 (2017-09-26, VHDL, 18375KB, 下载5次)
http://www.pudn.com/Download/item/id/1506389081639292.html
对vhdl的出租车计价器的设计,自己编写的,有详细的解释和说明,论文附有代码
Taximeter on the design of VHDL, written by itself, there are detailed explanations and notes, papers with code (2017-07-11, VHDL, 2163KB, 下载2次)
学生练习3—8译码器行为级 verilog 代码
Students practice the 3 - 8 decoder behavioral level Verilog code (2017-06-17, VHDL, 4249KB, 下载1次)
本人毕业设计使用加速度传感器做的双轴加速度测试,是LABVIEW编写
SO GOOD (2009-12-02, VHDL, 11KB, 下载30次)
代码实现了一个由32位寄存器组成的寄存器组,并有多个控制输入和两个输出,方便使用。
The code implements a 32-bit register consisting of registers, and there are multiple control inputs and two outputs, easy to use. (2009-10-23, VHDL, 10KB, 下载8次)
利用红外发射器和接收器 使小车能够沿着地面上的黑线循迹前进
Car that can follow the black lines using the sensors (2009-09-13, VHDL, 1425KB, 下载15次)
分频器,这是一个特殊的分频器。有不同的频率。可以选择。
Divider, which is a special divider. Have different frequencies. To choose from. (2009-08-25, VHDL, 336KB, 下载3次)
SDRAM控制器源代码,已经过调试,可以试用一下。
SDRAM controller source code, has been testing, you can try. (2009-06-24, VHDL, 7KB, 下载10次)
SDRAM控制器HDL实现,sdram为美光公司的
sdram controller (2009-06-15, VHDL, 3KB, 下载19次)
以太网控制器MAC的verilog代码,已经过验证,可以用。
Ethernet Controller (2009-05-25, VHDL, 88KB, 下载20次)
带有异步复位和同步时钟的十进制加法计数器
With asynchronous reset and synchronous clock counter decimal adder (2008-05-29, VHDL, 1KB, 下载22次)