DDS波形发生器下载搜索联合开发网

[VHDL/FPGA/Verilog] pulse_detector_HDL-Coder-Self-Guided-Tutorial

Mathworks HDL编码器教程，
Mathworks HDL Coder Tutorial, (2020-05-07, matlab, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1694141298960875.html

[VHDL/FPGA/Verilog] hdlcoder-examples

研究MatLab HDL编码器工具的示例。，
Examples to investigate MatLab HDL Coder tool., (2022-02-18, matlab, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1694141283564302.html

[VHDL/FPGA/Verilog] Wienerfilter

自适应维纳FIR滤波器消除脑电波中的干扰，请高手指教
Adaptive Wiener FIR filter brain waves to eliminate the interference, experts advise (2013-08-18, matlab, 4KB, 下载8次)

http://www.pudn.com/Download/item/id/2333027.html

[VHDL/FPGA/Verilog] ECG

心电信号的预处理滤波器的设计（包括数据文件和程序）包括了FIR滤波器和IIR滤波器以及整系数滤波器，可以有效滤除基线漂移与工频干扰
ECG preprocessing filter design (including data files and programs) including FIR filter and IIR filters, and the whole coefficient filter can effectively filter out baseline drift and frequency interference (2013-06-17, matlab, 286KB, 下载97次)

http://www.pudn.com/Download/item/id/2280763.html

[VHDL/FPGA/Verilog] ButterworthPrototypeToRealHPFilter

给定设计指标，由巴特沃斯滤波器的原型到实际滤波器的设计
Given design specifications, by the design of the prototype of the Butterworth filter to the actual filter (2013-03-29, matlab, 1KB, 下载4次)

http://www.pudn.com/Download/item/id/2178913.html

[VHDL/FPGA/Verilog] Program_9_2_py

基于切比雪夫1型滤波器以及双线性变换法的IIR滤波器设计。
IIR filter design based on the Chebyshev type 1 filter, and bilinear transformation method of IIR filter design. (2012-12-14, matlab, 1KB, 下载4次)

http://www.pudn.com/Download/item/id/2083112.html

[VHDL/FPGA/Verilog] full_pass_filter

设计一个全通滤波器，输入是一个正弦波，输出是90度的正弦波。
designed one full pass filter and input one sine wave and ouput one 90 degree sine wave (2012-12-01, matlab, 11KB, 下载75次)

http://www.pudn.com/Download/item/id/2067676.html

[VHDL/FPGA/Verilog] xianguanyulvbo

相关滤波器，用一个参考信号将淹没在噪声中的有用信号提取出来。
Correlation filter, with a reference signal will be drowned in the noise of the useful signal is extracted. (2012-10-30, matlab, 1KB, 下载23次)

http://www.pudn.com/Download/item/id/2031544.html

[VHDL/FPGA/Verilog] FIR-filter-design

窗函数法设计滤波器详细介绍，绝对原创，精心力作，有源码和word介绍
Window function design filter details, absolutely original, well-masterpiece, a source and word introduction (2012-10-19, matlab, 485KB, 下载5次)

http://www.pudn.com/Download/item/id/2020394.html

[VHDL/FPGA/Verilog] cic_compensating

CIC 补偿滤波器。采用两种方法来设计，一个是frequency sampling method。另一个是Equal Rippler Design Method。这是一个非常有用的matlab代码。
CIC compensation filter. Two ways to design a frequency sampling method. The other is an Equal Rippler Design Method. This is a very useful matlab code. (2012-10-17, matlab, 2KB, 下载56次)

http://www.pudn.com/Download/item/id/2018508.html

[VHDL/FPGA/Verilog] tx_ps

发射端....成形滤波器....实现代码
Transmitter .... shaping filter .... the implementation code (2012-08-07, matlab, 1KB, 下载20次)

http://www.pudn.com/Download/item/id/1960209.html

[VHDL/FPGA/Verilog] 1eziiir_matll6

16位iir滤波器Mtalab源码介绍，16位iirr滤波器Mtalab源码介绍可直接使用。已通过测试。
16 iir filter Mtalab source, 16 iirr filter Mtalab source describes can be used directly. Has been tested. (2012-07-17, matlab, 61KB, 下载3次)

http://www.pudn.com/Download/item/id/1940225.html

[VHDL/FPGA/Verilog] work

自己写的一段关于ECG滤波器的代码，陷波后低通，在高通滤波
Code they write a paragraph on the ECG filter low-pass, notch, high pass filter (2012-07-02, matlab, 33KB, 下载9次)

http://www.pudn.com/Download/item/id/1928142.html

[VHDL/FPGA/Verilog] EDA-fenpinqi

EDA多级分频器图形设计，频器输入频率为10 MHz,输出频率为1 Hz。分频器顶层图形文件设计、例化模块图形文件设计。
Multi-level divider graphic design, frequency input frequency of 10 MHz, the output frequency of 1 Hz. Divider top-level design of graphics files, for example, graphics files of the module design. (2011-12-23, matlab, 33KB, 下载5次)

http://www.pudn.com/Download/item/id/1739739.html

[VHDL/FPGA/Verilog] CPLDCARLIGHTSCONTROL

本课程设计根据计算机中状态机原理，采用CPLD技术设计了简易的汽车尾灯控制器。
This course is designed based on a computer, the state machine is designed cpld technology of the taillights controller. (2011-06-16, matlab, 6KB, 下载6次)

http://www.pudn.com/Download/item/id/1571524.html

[VHDL/FPGA/Verilog] daima

2选一功能选择器！加法器，8选一等，一个个简单却很常用的单个模块！
2 Select a function selector! Adder, 8-to-first-class, a simple single module is very popular! (2011-05-17, matlab, 7KB, 下载5次)

http://www.pudn.com/Download/item/id/1534990.html

[VHDL/FPGA/Verilog] fir_gen

fIR（有限冲击响应）滤波器基于vhdl语言开发
FIR filter (2010-05-21, matlab, 1KB, 下载2次)

http://www.pudn.com/Download/item/id/1181985.html

[VHDL/FPGA/Verilog] DesigningIIRFiltersPoint

IEEE文章仿真FIR滤波器,附带源代码程序,便于理解与深入学习.
IEEE article Simulation FIR filter, attached to the source code procedures, facilitate the understanding and in depth learning. (2007-11-17, matlab, 99KB, 下载21次)

http://www.pudn.com/Download/item/id/362052.html

[VHDL/FPGA/Verilog] qiangdaqi

用VHDL设计的7人的抢答器,优点是代码简单,特别适合初学着作为练习和增强代码编写能力的练习,好处
Designed using VHDL Answer 7 people, and the advantages of the code is simple, particularly suitable for the beginner as coding exercises and strengthen the capacity of exercises, the benefits of (2007-10-31, matlab, 1KB, 下载28次)

http://www.pudn.com/Download/item/id/353512.html

[VHDL/FPGA/Verilog] exa130302_cd

滤波器的设计IIR型 MATLAB语言实现
IIR Filter Design- MATLAB (2007-05-20, matlab, 1KB, 下载3次)

http://www.pudn.com/Download/item/id/285174.html