用verilog实现的全流水线risc-v处理器并在FPGA板上测试
A fully pipelined risc-v processor implemented in verilog and tested on an FPGA board (2023-11-26, Verilog, 0KB, 下载0次)
基于risc v的体系结构，用于开发能够矩阵MAC操作的核心处理器，
A risc v based architecture to develop a core processor which is capable of Matrix MAC Operations, (2023-07-31, Verilog, 0KB, 下载0次)
基于哈佛架构的MIPS处理器。单周期微体系结构在上执行整个指令...
MIPS processor based on Harvard Architecture. The single-cycle microarchitecture executes an entire instruction in one cycle. In other words instruction fetch, instruction decode, execute, write back, and program counter update occurs within a single clock cycle. (2022-03-09, Verilog, 83KB, 下载0次)
该项目包含基于RISC-V指令子集的32位处理器的详细实现...
This projects contains a detailed implementation of a 32-bit processor based on a subset of instructions from RISC-V ISA. The Micro-architecture contains 5 pipeline stages namely Fetch, Decode, Execute, Memory and Write back. Additionally, it also has a MAC execution unit to handle MAC instructions which are not part of RISC-V ISA. (2022-12-01, Verilog, 732KB, 下载0次)
单循环RISC-V处理器，带四级管道，无危险控制单元
Single cycle RISC-V processor with four stage pipeline without hazard control unit (2021-11-16, Verilog, 7KB, 下载0次)
RV32E201X是一个5级流水线32位RISC-V处理器内核。
RV32E201X is a 5-stage pipelined 32-bit RISC-V processor core. (2023-05-01, Verilog, 21554KB, 下载0次)
基于RISC-V ISA的单周期处理器。支持R型、lw、sw和beq指令。
Single Cycle Processor based on the RISC-V ISA. Supports R-type, lw, sw, and beq instructions. (2021-06-15, Verilog, 405KB, 下载0次)
具有包括高速缓存的内存子系统的单周期类MIPS处理器。
Single-cycle MIPS-like processor with a memory subsystem including a cache. (2023-06-08, Verilog, 22583KB, 下载0次)
使用FPGA在RISC-V CPU上尽可能快地计算卷积层的AI加速器。
AI Accelerator that computes as fast as possible a Convolutional Layer on a RISC-V CPU, using an FPGA. (2022-11-02, Verilog, 66KB, 下载0次)
基于RISC-VRV32I微处理器的Verilog实现（经典的5级，按顺序，单问题）
A Verilog implementation of a RISC-V RV32I based microprocessor (classic 5-stage, in-order, single issue) (2023-05-01, Verilog, 86KB, 下载0次)
针对特定于应用程序的资源稀缺软核CNN处理器的RISC-V ISA扩展（2022）
Extension to RISC-V ISA for an Application-Specific Resource-Scarce Soft-Core CNN Processor (2022) (2022-10-18, Verilog, 5451KB, 下载0次)
具有RISC-V ISA的32位处理器。采用Verilog设计，与DE2-115 FPGA兼容。
32-bit processor with a RISC-V ISA. Designed in Verilog to be compatible with the DE2-115 FPGA. (2023-01-19, Verilog, 119KB, 下载0次)
在Verilog中实现的单周期处理器。ENG EC413最终项目-计算机组织（2019年秋季）。
A single cycle processor implemented in Verilog. Final Project for ENG EC413 - Computer Organization (Fall 2019). (2019-12-04, Verilog, 37KB, 下载0次)
集成Berkeley hardfloat的,可以直接用于RISC-V处理器单精度FPU实现的小模块
A small module integrated with Berkeley hardfloat, which can be directly used for RISC-V processor single precision FPU implementation (2023-04-18, Verilog, 0KB, 下载0次)
一种面向安全的SoC，具有定制流水线RISC-V内核和LCD-TFT控制器
A security oriented SoC featuring a custom pipelined RISC-V core and LCD-TFT controller (2020-12-26, Verilog, 30959KB, 下载0次)
用于RISC-V CPU、加速器和存储系统架构研究的AWS-FPGA测试平台
An AWS-FPGA Testbed for Architecture Research on RISC-V CPUs, Accelerators, and Memory Systems (2023-02-27, Verilog, 9407KB, 下载0次)
用于公共访问的无默认Ravenna RISC-V处理器芯片设计文件的轻量级版本
A lightweight version of the efabless Ravenna RISC-V processor chip design files for public access (2021-07-29, Verilog, 12247KB, 下载0次)
基于融合通用神经网络（FuNN）的RISC-V火箭芯片捆绑式助推器
RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine (2022-03-17, Verilog, 10284KB, 下载0次)
基于SERV的SoC，Olof Kindgren的位串行RISC-V处理器。从Flash提供就地执行（XiP）。
SoC based on SERV, Olof Kindgren s bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash. (2020-09-10, Verilog, 33KB, 下载0次)
选择最大的输入，最后输出最大的数据，这个程序是在校研究生写的
Select the largest input, and finally output the largest data. This program is written by graduate students in school (2020-03-31, Verilog, 94KB, 下载0次)