在这个存储库中，我使用Verilog介绍了一个2级流水线Risc-V处理器的实现，并与它一起构建了一个汇编程序，以使编写程序变得更容易，因此您可以在指令存储器上编写程序并执行它。
In this repository, I introduced an implementation of a 2-stage pipelined Risc-V Processor using Verilog and built an Assembler along with it to make it easier to write programs so you can write them on the instruction memory and execute it. (2024-04-05, Verilog, 0KB, 下载0次)
在主动HDL程序中，在Verilog中设计并验证了一个简单的流水线RISC处理器。
Design and verify a simple pipelined RISC processor in Verilog in Active HDL program. (2024-03-26, Verilog, 0KB, 下载0次)
该项目构建处理器的简单版本，足以实现RISC-V32I指令的特定子集
This projects constructs a simple version of a processor sufficient to implement a specific subset of RISC-V32I instructions (2024-03-25, Verilog, 0KB, 下载0次)
使用verilog HDL设计了一个“路由器”，将数据传输到3个不同的目标设备。
A "Router" has been designed using verilog HDL which transfers data to 3 different destination devices. (2024-02-05, Verilog, 0KB, 下载0次)
一种可以执行RV32I基本指令集的5级流水线RISC-V处理器的设计与实现
Design and implementation of a 5-stage pipelined RISC-V processor that can execute the RV32I base instruction set (2023-11-26, Verilog, 0KB, 下载0次)
实验性开源CPU，带指令解码器、ALU（加法、减法和或、非、异或、rotL、rotR）、乘法器、除法器等。。
experimental open source CPU with instruction decoder, ALU (add, sub, and, or, not, xor, rotL,rotR), multiplier, divider, etc.. (2023-11-05, Verilog, 0KB, 下载0次)
具有内部FIFO缓冲器的通用全双工RS232 FPGA模块，
A versatile full-duplex RS232 FPGA module with interfnal FIFO bufer, (2023-06-25, Verilog, 0KB, 下载0次)
三态以太网MAC控制器，支持10M/100M/1000M三种速率，采用wishbone总线
Three state Ethernet MAC controller, supporting 10m / 100M / 1000m three rates, using wishbone bus (2020-12-12, Verilog, 1135KB, 下载1次)
对时钟进行奇数分频，实现奇数得占空比为50%得分频
Carry on odd frequency division to the clock, realize the odd duty ratio is 50% score frequency (2020-09-15, Verilog, 1348KB, 下载0次)
计算机处理器设计，第一条指令的实现，各模块代码及测试文件
Computer processor design, implementation of the first instruction, module code and test file (2019-12-12, Verilog, 4KB, 下载2次)
组合时序电路的小例子，移位和数据选择器的代码，以及测试文件
Small examples of combinational sequential circuits, code for shift and data selectors, and test file. (2019-12-12, Verilog, 57KB, 下载1次)
基于AHB BUS的SRAM 控制器（带有Mbist单元）
Practice project of ahs-sram: SRAM controller based on AHB bus (with MBIST unit) (2019-10-27, Verilog, 1482KB, 下载2次)
CFI控制器顶层模块，32位wishbone总线经典接口，用于简化对CFI flash(如块)的访问解锁、删除和编程。
Top level of CFI controller with 32-bit Wishbone classic interface (2019-07-31, Verilog, 4KB, 下载1次)
用于配置ov5640寄存器，平台为quartus13，芯片为cycloneIV
The file is used to configure the ov5640 register. The platform is quartus 13 and the chip is cyclone IV. (2019-04-12, Verilog, 12KB, 下载3次)
很好的教程，适用于刚开始进行fpga学习的小白，帮助很大
Very good tutorial, suitable for the beginning of FPGA learning Xiao Bai, help a lot (2018-09-30, Verilog, 376KB, 下载2次)
实现3-8译码器,有效的降低复杂度，基础学习非常实用，必备技能
it is useful to decoder the bin (2018-05-02, Verilog, 1703KB, 下载6次)
用于控制外部sdram，是fpga连接外部sdram的桥梁，希望对大家有用
For controlling external SDRAM, it is a bridge for FPGA to connect external SDRAM. It is useful for everyone. (2018-04-16, Verilog, 8KB, 下载1次)
完成了264编码器的编码功能，在modelsim上仿真，可以通过
The encoding function of the 264 encoder is completed, which is simulated on the Modelsim and can be passed through (2017-12-28, Verilog, 8209KB, 下载5次)
格雷码计数器实质包含了三个部分 格雷码转二进制、加法器、二进制转格雷码。通过quartus II 自带的Modlesim仿真验证了 能够实现二进制和格雷码之间的转换
Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II verified to achieve the conversion between binary and gray code (2017-12-11, Verilog, 2908KB, 下载3次)
mux四选一及译码器：MUX电路在数字集成电路被广泛使用，作为寄存器或者其他电路的输入选择控制。也是ASIC设计中的基本门电路之一。
MUX four selection one and decoder (2017-12-06, Verilog, 2KB, 下载2次)