[DSP编程] OMAPL138和FPGA的合并单元设计方案
提出了一种基于 ＡＲＭ９＋ＤＳＰ双核处理器 ＯＭＡＰＬ－１３８和 ＦＰＧＡ 的合并单元设计方案。给出了该方案的原理框图，以及具体的程序流程图，并在 ＣＣＳ开发环境下完成了软件编程，实现了合并单元按照ＩＥＣ６１８５０标准规定的格式进行数字量以太网传输。实验结果证明了该设计方案的可行性与正确性，为合并单元的设计提供了一种新的思路。
A design scheme of combining unit based on ARM9+DSP dual-core processor OMAPL-138 and FPGA is proposed. The schematic block diagram and the flow chart of the program are given. The software is programmed under the CCS development environment. The merging unit can transmit digital data over Ethernet according to the format specified in IEC61850 standard. The experimental results prove the feasibility and correctness of the design scheme, and provide a new idea for the design of merging unit. (2018-09-01, Others, 161KB, 下载1次)
[DSP编程] DSP-tec
首先介绍了嵌入式DSP系统的基本硬件,然后着重说明用C语言进行硬件编程的好处和基本方法,包括如何调试C
语言程序,最后介绍了如何将C语言程序转化为DSP代码。所有内容均基于TI公司的TMS320C55x通用DSP芯片,使用的软件工具是该公司的CCS集成开发环境(IDE)。
First introduced the embedded DSP system' s basic hardware, and then use the C language highlighting the benefits and basic hardware programming methods, including how to debug C language program, and finally describes how the C language program into DSP code. All content is based on TI' s TMS320C55x DSP chip general, the use of software tools is the company' s CCS integrated development environment (IDE). (2013-07-03, Others, 83KB, 下载2次)
[DSP编程] DSP_FPGAcontrol232
传统的DSP 控制通常针对的是三相系统,其外设资源不能满足多相逆变器的控制要求,文中
提出一种DSP + FPGA 的控制器解决方案. 特别利用了FPGA 逻辑资源丰富,编程灵活的特点,设
计了译码电路、脉冲发生、串口通信、看门狗保护、硬件状态锁存等功能单元,在有效扩展系统功能
的同时,降低了运算单元的负荷,提高了整体性能. 对设计进行了时序仿真,并将其应用于8 MW逆变器的控制系统中,结果验证了设计方案的功能性与可靠性.
Traditional DSP control is usually targeted at three-phase system, its peripherals resources can not meet the requirements of multi-phase inverter control, the paper presents a DSP+ FPGA controller solutions, especially the use of the FPGA logic resource-rich, flexible programming characteristics, the design of the decoding circuit, pulse, serial communication, watchdog protection, hardware, latches and other functional unit state, the effective expansion of system functions, while reducing the computing unit load, improve the overall performance of the design for timing simulation, and applied to 8 MW inverter control system, the results validate the design' s functionality and reliability. (2011-08-21, Others, 568KB, 下载19次)
[DSP编程] USB_AD
实验目的:学习DSP内部定时器0的使用 **
** 实验说明:本实验是通过使用DSP内部的定时器0来实现对LED灯的控制 **
** 大家在刚开始学习时最好先把我们所提供的课本上的第一,二, **
** 六章有个了解,然后在来学习.第一二章分别介绍了DSP的基本 **
** 组成,第六章讲了DSP的C语言编程风格 **
** 实验结果:可看到板上8个发光二极管奇数号LED与偶数号LED交替闪烁
Experimental purposes: to learn the use of the DSP internal timer 0**** experiment shows: In this study, by using the internal DSP timer 0 to achieve control of the LED light**** We just started learning the best in the first We provide books on the first, second, there was an understanding** six chapters, and then to learn the first two chapters introduced the basic**** form of DSP, the sixth chapter describes the DSP** C programming style results: you can see the board eight light-emitting diode LED and an even number odd number of LED flashes alternately (2011-07-21, Others, 5315KB, 下载4次)
[DSP编程] TMS320C54x_DSP_Design_Workshop
TI推出的价格昂贵的培训课程，这是TMS320C54x Design DSK Four-Day Workshop的培训课程的相应资料和例程。一共4天的培训的课程，对于C54x系列的DSP讲解的很透彻。关于C5416，TI公司推出了2次培训培训课程。这是课程之一，也就是没有使用DSP/BIOS.在课程之二－Intergrate Design才引入了DSP/BIOS编程。TI公司自己推出的培训计划，确实很有针对性，能让学习的人少走弯路！内部资料，贡献给大家，一起学习C5000 DSP！
TI introduced the expensive training courses, which is TMS320C54x Design DSK Four-Day Workshop training courses relevant information and routines. A total of 4-day training course, for the C54x DSP family is very thorough explanation. On the C5416, TI introduced the 2 training courses. This is one course, which is not using DSP/BIOS. In the course of the two-Intergrate Design before the introduction of the DSP/BIOS programming. TI launched its own training program, who are very specific, allowing people to learn fewer detours! Internal information, contribute to everyone learning together C5000 DSP! (2010-05-16, Others, 1228KB, 下载62次)
[DSP编程] DSP
本课题设计的是基于DSP的A429通信测试板。该测试板的设计实现了PC机与 ARINC429 协议通信系统间通讯的测试，采用 DSP 控制，利用 ARINC429总线接口芯片 HS3282,HS3182 和CPLD等，构成了一款结构简单、可靠性高的测试电路板。该测试板的逻辑控制电路通过对CPLD的编程实现，整个电路简单、紧凑。
The design of this subject is based on the DSP board communications test of the A429. The test board design to achieve a PC computer and communication systems ARINC429 communication protocol testing, the use of DSP control, the use of ARINC429 bus interface chip HS3282, HS3182 and the CPLD, which form a simple structure, high reliability and testing circuit boards . The test of the logic control circuit board, through the programming of CPLD, the entire circuit is simple, compact. (2009-07-17, Others, 1162KB, 下载58次)
[DSP编程] FIR
已知一低通滤波器的采样率为2KHz，通带为500Hz，阻带为600 Hz，带内波动3dB，带外衰减-50dB，滤波器的相位具有线性特性，具体幅频特性见下图。要求用等波纹方法设计出该FIR滤波器，然后用TMS320C54x汇编语言编程，并在CCS下调试实现该FIR滤波器。
A low-pass filter known to the sampling rate of 2KHz, passband to 500Hz, stopband to 600 Hz, with fluctuations within 3dB,-band attenuation of-50dB, with a linear phase filter characteristics, amplitude-frequency characteristic specific see Fig. Request method, such as corrugated design of the FIR filter, and then use the TMS320C54x assembly language programming and debugging in CCS to achieve the FIR filter. (2009-07-10, Others, 28KB, 下载50次)
[DSP编程] Lab07-Timer
DSP5416时钟配制，片内定时器是一个软件可编程定时器，可以用来产生周期的中断信号。 定时器主要由 3 个寄存器所组成：定时器寄存器（TIM） 、定时器周期寄存器（PRD）和时器控制寄存器（TCR） 。这 3 个寄存器都有映象寄存器，它们在数据存储器中的地址分别24H、25H 和 26H。TIM 是一个递减计数器；PRD 中存放计数值；TCR 中有定时器的控制和状态位
DSP 5416 timer configuring,A timepiece, especially one used for measuring and signaling the end of time intervals, as on a stove.
Four registers that function as a single register. In hardware, it often represents a register. For example, the B box, the subscript box. One register might contain status describing an error.A flag bit in the status register of the central processing unit, used to show a negative result from an arithmetic operation.Software running on the CPU must be able to read and write those controlling registers. However, the number of registers is severely limited, so registers are allocated by the compiler according to its needs. A register consisting of a flip flop which stores binary data. (2009-03-11, Others, 7KB, 下载13次)
[DSP编程] DSP_Max_Log_MAP
基于DSP平台实现turbo码Max_Log_MAP算法，基于标准C 语言研究
了Turbo 码Max - Log - MAP 译码算法的软件编程与实现,为了提高程序的运行效率,结合TMS320C6000 系列DSP 芯片
的结构与特点采用循环展开、数据的存取优化设计、算法改进等措施进行了代码优化,给出了测试结果，非常值得一看
DSP platform based on turbo code Max_Log_MAP algorithm, based on standard C language studied Turbo Code Max- Log- MAP decoding algorithm of the software programming and realize, in order to improve process efficiency, combined with TMS320C6000 DSP chip structure and characteristics of the use of cycle start the design of data access optimization, algorithms and other measures to improve the code optimization, are given the test results, very worth a visit (2008-01-30, Others, 306KB, 下载118次)