欢迎来到#50DaysVerilogWithMeGitHub存储库，在那里我们开始了一次为期50天的Verilog编程全面旅程。该计划旨在为参与者提供Verilog（一种广泛用于数字设计的硬件描述语言）的结构化增量学习体验。
Welcome to the #50DaysVerilogWithMe GitHub repository, where we embark on a comprehensive 50-day journey into Verilog programming. This initiative is designed to provide participants with a structured and incremental learning experience in Verilog, a hardware description language widely used in digital design. (2024-02-04, Verilog, 0KB, 下载0次)
在本项目中，使用Verilog开发了一种复杂的交通灯控制器，并在FPGA（现场可编程门阵列）平台上实现。主要目标是使用摩尔状态机设计范例模拟真实的交通管理系统。
In this Project, a sophisticated traffic light controller was developed using Verilog and was implemented on an FPGA (Field-Programmable Gate Array) platform. The primary aim was to simulate a realistic traffic management system, employing a Moore state machine design paradigm. (2023-12-29, Verilog, 0KB, 下载0次)
这是一款电脑游戏，具有侧滚滚动式界面，用Verilog编程。一旦烧毁到FPGA板中，它可以是co...，
This is a computer game with a side-scrolling scroll-style interface, programmed in Verilog. Once burned into an FPGA board, it can be connected to a computer screen and keyboard to start an exciting and thrilling gaming experience. (2023-08-10, Verilog, 0KB, 下载0次)
VHDL（Verilog硬件描述语言）是一种可以用来模拟硬件电路的编程语言
VHDL(Verilog Hardware Description Language) is a programming language using which one can simulate hardware circuits (2020-07-30, Verilog, 99KB, 下载0次)
这项工作实现了一种用于执行局部序列比对的动态编程算法。通过并行，它...
This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm. (2019-07-04, Verilog, 12947KB, 下载0次)
Home Brew 8位CPU硬件实现，包括Verilog模拟、汇编程序、“C”编译器和此代表...
Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. <https://hackaday.io/project/166922-spam-1-8-bit-cpu> (2022-09-09, Verilog, 179722KB, 下载0次)
一位加法器，实现两个一位二进制的相加，有进位输入，输出，很好用，自己写的第一个
One bit adder, which can add two bits and one bit binary. It has carry input and output. It is easy to use. The first one written by oneself (2020-04-04, Verilog, 1KB, 下载0次)
本文研究的IIC总线控制器具有如下特征
1.兼容飞利浦I2C标准，以主机模式与外围设备进行数据通信，对IIC从机模型进行读/读，读/写，写/写，写/读[18]。
2.多主操作
3.软件可编程时钟频率
4.时钟拉伸和等待状态生成
5.软件可编程确认位
6.时钟同步设计
7.仲裁中断丢失，自动转移取消
8.开始/停止/重复启动检测/确认生成
9.总线忙检测
The IIC bus controller studied in this paper has the following characteristics.
1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18].
2. Multiple Main Operations
3. Software programmable clock frequency
4. Clock stretching and waiting state generation
5. Software Programmable Confirmation Bit
6. Clock Synchronization Design
7. Loss of arbitration interruption and cancellation of automatic transfer
8. Start/Stop/Repeat Start Detection/Verification Generation
9. Bus busy detection (2019-06-18, Verilog, 1486KB, 下载2次)
FPGA设计指导和编程设计环境介绍，是FPGA设计很好的参考资料
The design guidance and programming environment of the FPGA are good references for the design of the FPGA. (2019-05-17, Verilog, 2129KB, 下载1次)
FPGA开发全攻略，主要运用Verilog硬件描述语言，进行FPGA编程开发，资料内容丰富详尽
The full strategy of the development of FPGA is mainly based on Verilog Hardware Description Language. The data is rich and detailed. (2019-04-18, Verilog, 26873KB, 下载4次)
在 FLASH 读写测试程序中我们需要实现 FLASH 的设备 ID 的读取，Sector 擦除，Page 编程，数据的读取这四大块的功能
In FLASH read and write test program, we need to realize the functions of reading device ID, Sector erase, Page programming and data reading of FLASH. (2019-03-30, Verilog, 1645KB, 下载5次)
可编程数字系统设计的基本流程
设计输入（原理图文件、硬件描述语言文件、网表输入文件、混合输入文件）项目处理（设计文件检查和编译、设计文件分析和综合、器件适配、设置设计约束）设计校验（生成功能网表、功能仿真、适配后的仿真文件、门级时序仿真）器件编程（生成器件编程文件、器件编程）
原理设计输入方式是利用软件提供的各种原理图库，采用画图的方式进行设计输入。这是一种最为简单和直观的输入方式。原理图输入方式的效率比较低，一般只用于小规模系统设计，或用于在顶层拼接各个已设计完成的电路子模块。
Basic Flow of Programmable Digital System Design
Design Input (schematic diagram file, hardware description language file, netlist input file, mixed input file) project processing (checking and compiling design documents, analysis and synthesis of design documents, device adaptation, setting design constraints) design verification (generating functional netlist, function simulation, adapted simulation files, gate-level timing simulation) device programming (generating component programming text) Programming of Components and Devices
Principle design input mode is to use various schematic library provided by the software to design input by drawing. This is the simplest and most intuitive way to input. The input mode of schematic diagram is inefficient. It is usually only used for small-scale system design or for splicing each completed circuit sub-module at the top level. (2018-12-24, Verilog, 6632KB, 下载1次)
用verliog进行编程，用数码管显示0~F16进制数码循环，并显示对应的流水灯样式
Programming with verliog, using the digital tube to display 0~F16 digit digital loop, and display the corresponding stream light style. (2018-07-01, Verilog, 13KB, 下载2次)
这是一个使用Vivado开发，使用Verilog编程实现，包含testbench和约束文件。
This is a program developed by using Vivado platform. Using Verilog programming, including testbench and constraint files. (2018-05-22, Verilog, 903KB, 下载13次)
adv7123是常用的视频解码器，常常可用fpga编程控制，使其输出ntsc、pal制式，或者vga显示，这里面全是关于这方面的论文，很值得借鉴参考。
Adv7123 is a commonly used video decoder. It can often be controlled by FPGA programming, so that it can output NTSC, PAL format or VGA display, which is all about the papers in this area, so it is worth learning from for reference. (2018-01-20, Verilog, 17111KB, 下载30次)
1.硬件平台： FPGA；
2.编程语言： Verilog；
3.串口通信RS232的Verilog实现版本；
1. hardware platform: FPGA;
2. programming language: Verilog;
The Verilog implementation version of 3. serial port communication RS232; (2018-01-11, Verilog, 55KB, 下载5次)
在开发板EGO1上实现的小鸟游戏，有详细地模块说明，使用vivdao平台实现
Bird board game on the development board EGO1, a detailed module description, the use of vivdao platform (2017-12-13, Verilog, 510KB, 下载47次)
一些对初学者比较实用的源码，ASK，PSK，FSK调制解调
Some of the more practical source code for beginners (2017-10-15, Verilog, 1251KB, 下载52次)
使用Altera FPGA平台，Verilog编程语言，编写步进电机驱动程序，已在开发板上验证；
on altera fpga flatform, use verilog language, driving stepmotor, and test ok. (2017-10-08, Verilog, 300KB, 下载20次)