基于FPGA的数字电子钟设计，系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时，显示满刻度为23时59分59秒，另外有校时、校分和整点报时功能，并通过数码管驱动电路显示计时结果。
FPGA-based design of digital electronic clock, the system program by the total frequency module, " the minutes and seconds" counter module, data selection module, timer module, dynamic scanning display and decoding module. Get a will " ," and " division" and " seconds" display on the human visual organ of the timing device. It' s time for the 24-hour period, indicating full scale as 23:59:59, and another school, the school hours and the whole hour, and through digital tube display driver circuit timing results. (2010-04-07, VHDL, 62KB, 下载27次)
这是一个基于FPGA设计的24时多功能数字钟，具有正常星期、时、分、秒计时，动态显示，保持、清零、快速校分、整点报时、闹钟功能。
This is an FPGA-based design of multi-function digital clock 24 hours, with a normal week, hours, minutes, seconds, timing, dynamic display, maintaining, resetting, fast school hours, the whole point timekeeping, alarm clock function. (2010-03-06, VHDL, 773KB, 下载27次)
这是我电子线路测试的作业，在FPGA板上实现数字钟，（Max2环境）采用VHDL语言编写，非常适合初学者。具备24小时计时，校时，低高音整点报时，定时和多重功能选择的功能。
This is my test of electronic circuits operating at the FPGA board digital clock (Max2 Environment) using VHDL language, very suitable for beginners. 24-hour time, the school, the whole point of low Treble timekeeping, the timing and choice of multiple functional function. (2007-01-31, MultiPlatform, 495KB, 下载26次)
用VHDL语言编写的一个乘法器校程序
是基于BOOTH算法的
VHDL language using a multiplier BOOTH school program is based on the algorithm (2008-05-22, VHDL, 1KB, 下载25次)
s1. 所设计数字钟具有“时”、“分”、“秒”的十进制数字显示（小时从00～23）。
2. 可以进行手动校时、校分功能。
3. 能进行整点报时。从59分51秒开始每隔2秒钟连续发出四次低音“嘟。嘟、嘟、嘟”，，最后一次发出高音“嗒”。此信号响起时即达整点。
you can see see (2009-12-03, VHDL, 157KB, 下载24次)
这是本人在学校做的一个DDS信号发生器，频率相位可调。输入时钟50Mhz
DDS phase frequency adjustable Verilog (2015-07-29, VHDL, 2380KB, 下载22次)
这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。
This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off. (2009-09-15, HTML, 1017KB, 下载20次)
可实现校时，仿电台报时，闹钟，报整点时数
The school can be realized when the fake radio timekeeping, alarm clock, reported that the number of hours the whole point of (2009-12-30, VHDL, 13KB, 下载18次)
两个按键控制校时的VHDL时钟源码，带定时闹钟和日历功能
Two buttons control the school at the time of VHDL source clock, alarm clock and calendar with timing function (2008-07-11, VHDL, 2KB, 下载17次)
以前学习VHDL语言时做的一个电子闹钟程序，可以实现时，分，秒的计时以及定时，校时，闹钟，整点报时的功能。
VHDL language before learning to do procedures in an electronic alarm clock, you can realize hours, minutes and seconds of time and from time to time, school time, alarm clock, the whole point timekeeping function. (2008-09-25, VHDL, 166KB, 下载13次)
这时用VHDL语言编写的多功能数字钟，具有正常的计时功能，还能进行校时、校分，并且具有整点报时功能
Then with the VHDL language multi-functional digital clock, with the normal timing functions, but also to the school, the school hours, and have the whole point timekeeping function of (2009-09-22, VHDL, 445KB, 下载13次)
实验利借助于Quartus II 软件设计了一个多功能数字钟，实现了校时，校分，清零，保持和整点报时等多种基本功能，此外还实现了闹钟，星期，音乐闹铃等附加功能。本文首先利用Quartus II进行原理图设计并仿真调试，最后在实验板上验证了设计的正确性。
关键字：数字钟 闹钟 仿真 准点报时
Quartus II software by means of experimental Lee designed a multi-functional digital clock and realized the school, the school hours, cleared, and the whole point of time keeping and other basic functions, in addition to achieve the alarm clock, week, music, alarm, etc. Additional function. This paper carried out using Quartus II schematic design and simulation debugging, and finally verified in the experimental board design is correct. Keywords: digital clock alarm clock simulation of quasi-point of time (2010-05-08, VHDL, 1158KB, 下载13次)
① 用EDA实训仪的I/O设备和PLD芯片实现数字日历的设计。
② 数字日历能够显示年、月、日、时、分和秒。
③ 用EDA实训仪上的8只八段数码管分两屏分别显示年、月、日和时、分、秒，即在一定时间段内显示年、月、日（如20080101），然后在另一时间段内显示时、分、秒（如00123625），两个时间段能自动倒换。
④ 数字日历具有复位和校准年、月、日、时、分、秒的按钮，但校年和校时同用一个按钮，即在显示年、月、日时用此按钮校年，在显示时、分、秒时则用此按钮校时，依此类推。
① The EDA training instrument I/O devices and PLD chip digital calendar design.
② Figures calendar can display year, month, day, hours, minutes and seconds.
③ instrument training with EDA eight out of eight two-screen digital display, respectively, year, month, day and hour, minute, second, that a certain period of time shows year, month, day (eg 20080101), then another period of time shows hours, minutes, seconds (eg, 00123625), automatically switching the two time periods.
④ reset and calibrated with a digital calendar year, month, day, hour, minute, second button, but when the school year and school with a button that displays the year, month, day use this button when the school year, when the display , minutes, seconds, use this button to school, and so on.
(2011-06-22, Others, 4878KB, 下载12次)
本文介绍了一个多功能电子钟的设计方案。该方案具有计时、整点报时、校时、校分、闹钟等多项功能。此方案基于Altera 公司的 Cyclone 芯片及Quartus II 7.2 软件。整体设计采用自顶向下的设计思想，大量使用了器件模块化操作。本文对于研究数字钟及扩大其应用，有着非常现实的意义。
This paper describes a multi-clock design. The program has the time, the whole point of time, school hours, school hours, alarm clocks and many other features. This program is based on Altera' s Cyclone chip and Quartus II 7.2 software. The overall design using top-down design, extensive use of modular operation of the device. This digital clock for research and expand its application, has a very practical significance. (2010-09-08, VHDL, 756KB, 下载12次)
基于FPGA的数字时钟，能校时、校分，整点报时。
fpga clock (2012-03-02, VHDL, 316KB, 下载12次)
基于basys2的简易数字钟，包含校时功能
A simple digital clock base on basys2 board, including timing function. (2016-05-13, Others, 414KB, 下载11次)
多功能数字钟，实现了计时、校分、闹钟、日历等功能，已通过仿真验证
Multifunction digital clock, to achieve the timing, the school points, alarm clock, calendar and other functions, has been verified by simulation (2011-09-23, VHDL, 1251KB, 下载10次)
数字钟verilog程序，实现了校时、闹钟校正、整点报时、当前时间与闹钟时间切换显示功能。
Digital clock verilog program, school, alarm clock correction, the whole point timekeeping function. (2012-12-15, VHDL, 100KB, 下载10次)
数字电路时间以12小时为一个周期，显示时、分、秒，具有校时功能，可以分别对时及分进行单独校时，使其校正到标准
时间计时过程具有报时功能，当时间到达整点前10秒进行蜂鸣报时
SHUZISHIZHONG (2012-12-10, MultiPlatform, 3873KB, 下载10次)
多功能数字时钟课程设计可用的,含手动校时电路，整点报时电路。报时长短需要自己设置程序
digital clock decode (2010-04-24, VHDL, 1KB, 下载9次)