利用QuartusII7.0、MATLAB以及SmartSOPC实验系统进行多功能数字钟的设计是本次试验的主要内容。该数字中需包含的功能主要有：分频、校时校分、清零、动态显示、整点报时、闹钟闹铃、秒表以及24小时制和12小时制的转换等。
QuartusII7.0, MATLAB, and SmartSOPC experimental system for the design of multi-function digital clock is the main content of the trial. The figure is included in the functions needed are: sub-band, school, when school hours, resetting, dynamic display, the whole point timekeeping, alarm clock alarm, stopwatch and 24-hour system and 12-hour system conversion. (2011-06-08, VHDL, 249KB, 下载9次)
基于FPGA的数字万年历设计。可显示年月日时分秒星期，可校时，可整点报时。
FPGA-based design of digital calendar. Displays the date when the minutes and seconds the week, when the school can be the whole point timekeeping. (2016-06-27, VHDL, 150KB, 下载8次)
采用可综合的Verilog代码编写一个带闹钟功能的数字钟。使其具有以下功能：
1)计时功能：包括小时、分钟、秒钟。
2)校时功能：对小时、分钟和秒钟进行手动校时。
3)定时和闹钟功能：能在手工设定的时间产生闹铃音。
Using synthesizable Verilog coding a digital clock with alarm. It has the following features:
1) timing functions include: hours, minutes, seconds.
2) When the school functions: hours, minutes and seconds to the manual correction.
3) timing and alarm functions: to produce an alarm sound at the set time manually. (2015-01-24, VHDL, 2KB, 下载8次)
设计一个多功能数字时钟:时钟显示，手动校时，整点报时，闹钟功能
Clock manually school, the whole point timekeeping, alarm clock function (2013-04-09, VHDL, 360KB, 下载8次)
数字钟设计 计时计数器用24进制计时电路；
可手动校时，能分别进行时、分的校正；
整点报时；
选做：可设置闹时功能，当计时计到预定时间时，扬声器发出闹铃信号，闹铃时间为4s，并可提前终止闹铃。
Digital clock design (2012-09-03, VHDL, 709KB, 下载7次)
数字钟，功能：12时/24时切换显示，校时,时间很准（4位数码管显示），内含sof，pof，tcl，四个文件，在开发板C1上已实现
digital clock ，verilog (2013-08-21, VHDL, 18KB, 下载7次)
数字时钟6位数码管显示。主要器件为74ls48和74ls160 /74ls161。功能：1.显示时、分、秒。2. 可以24小时制或12小时制。3. 具有校时功能
Digital clock six digital tube display. Main components of 74ls48 and 74ls160/74ls161. Features: 1. Shows hours, minutes, seconds. (2) a 24-hour or 12-hour clock. 3 a school function (2013-07-18, Others, 490KB, 下载7次)
用Verilog HDL 设计一个多功能数字钟，包含以下主要功能：
（1） 计时，时间以24小时制显示。
（2） 校时，
（3） 跑表：启动、停止、暂停
Verilog HDL design with a multi-functional digital clock, includes the following main functions: (1) time, time to 24-hour display. (2) school, (3) stopwatch: start, stop, pause (2010-12-02, VHDL, 1342KB, 下载7次)
电子钟的设计，(1) 计时功能：这是本计时器设计的基本功能，可进行时、分、秒计时，并显示。
(2) 闹钟功能：如果当前时间与设置的闹钟时间相同，则扬声器发出一段音乐，并维持一分钟。
(3) 调时调分调闹钟功能：当需要校时或者要重新设置闹钟的时间时，可通过实验箱上的按键控制。
The design of electronic clock, (1) timer function: This is the basic design of the timer function, can be hours, minutes, seconds, time, and displayed. (2) Alarm function: If the current time and set the alarm clock the same time, the speaker issued a piece of music, and to maintain a minute. (3) adjusting the tone when the tone alarm sub-functions: the school or when when you need to re-set the alarm time, the experimental box through the keys on the control. (2010-11-30, VHDL, 82KB, 下载7次)
闹钟、电子钟典型实例，具有校时，整点报时等功能
Alarm clock, electronic clock typical example, a school, the whole point of time and other functions (2010-04-25, VHDL, 245KB, 下载7次)
多功能数字钟实现闹铃，整点报时，校时，仿广播电台报时功能
multifuntional digital clock written in verilog (2010-02-12, VHDL, 1KB, 下载7次)
利用maxplus2完成
1、 完成带时、分、秒显示的24h计时功能；
2、 能完成整点报时功能，要求当数字钟的分和秒计数器计到59min52s时，驱动音响电路，四高一低，最后一声高声结束，整点时间到；
3、 完成对“时”和“分”的校时，并能对秒计数器清零。
Use maxplus2 completed one complete with hours, minutes, seconds, show 24h time functions 2, can complete the whole point timekeeping function, require that when the digital clock minutes, and seconds counter when the count to 59min52s, driver audio circuit, four high and one low, soon as the end of the last loud, the whole point of time to 3 to complete the " time" and " sub" when the school is also able to clear the seconds counter. (2009-11-01, WORD, 165KB, 下载7次)
这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用
When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design (2009-09-22, VHDL, 1KB, 下载7次)
基于FPGA的多功能数字钟系统（层次化设计）拓展功能包括：报时、校时校分、6到18点时段控制亮灯
Multi-functional digital clock system (hierarchical design) in the FPGA-based development features include: timekeeping, school Calibration of 6-18 hours to control lighting
(2012-05-17, VHDL, 560KB, 下载7次)
verilog写的时钟程序，带有校时和闹铃功能
clock program written with verilog (2012-02-25, VHDL, 2KB, 下载7次)
多功能数字钟 24小时计时 整点报时功能 闹钟设置功能 校时 复位等
Multi-function digital clock 24 hours to strike the alarm clock on the hour function when the reset function, etc (2012-01-05, VHDL, 11KB, 下载7次)
电子表的设计,包括正常计时模块，LED显示模块，定时报警模块，校时模块，秒表模块。
Electronic form design, including the normal timing module, LED display module, timing alarm module, timing modules, stopwatch modules. (2011-12-14, VHDL, 2KB, 下载7次)
用方波信号发生器发出1HZ的稳定的方波信号作为CP信号输入 ,秒计数器满60向分计数器进位,分计数器满60向小时进位,小时计数器按“23翻0”规律计数，计数器经译码器送到显示器；计数出现误差可用校时电路进行校时、校分、校秒。并具有可整点报时与定时闹钟的功能。
本数字钟的功能列表如下：
1）基本功能：秒、分钟、小时计时、显示及校对；
2）整点报时功能：在每小时59分50秒开始500Hz频率发声提示，整点时1000Hz发声，之后声音停止；
3）定时报闹功能：可设定闹钟定点报闹，可用开关关闭；
Square wave signal generator with a 1 HZ stability of square wave signal as CP signal input, counter full 60 seconds to points counter carry and points to counter full 60 hours carry and hours counter press "23 turn 0" rule count, the counter decoder to display Count serious error when the circuit can be used when the school, the school to points, the school to seconds. And has the time and timing of the alarm clock function.
The function of the digital clock listed below:
1) the basic function: seconds, minutes, hours timer, display and proofreading
2) hourly chime function: every hour on 59 points 50 seconds began to 500 Hz frequency voice prompt, the hour 1000 Hz uttered his voice, the voice after stop
3) set times make function: to set the alarm clock fixed-point report make, can be used to switch to shut down
(2012-03-20, Others, 675KB, 下载6次)
基于UP3borad开发板的时钟设计，可校时，设置闹钟等
Clock design based on UP3borad the development board, can the school, set the alarm (2012-05-23, VHDL, 354KB, 下载6次)
用verilog编写的闹钟程序，含闹钟设置，计时，校时模块。
With verilog write alarm clock program, including alarm, timing, when the module. (2012-05-17, Others, 392KB, 下载6次)