实现一个24小时制的数字时钟，可切换校时模式，带有闹钟和整点报时功能，约束文件基于basys2实验板
A 24-hour digital clock with alarm clock and full-time alarm function can be switched. The constraint file is based on the basys2 experimental board. (2018-12-30, Verilog, 36571KB, 下载3次)
数字钟，实现整点报时以及校时功能，烟大数字逻辑课程实验。
Digital clock, realize the whole point timekeeping and school function, smoke large digital logic course experiment. (2013-11-08, VHDL, 496KB, 下载3次)
多功能数字电子表
（１）正常计时：秒（60）、分（60）、小时（24）计数；秒计时的频率为1Hz，数码管用动态扫描实时显示计时的小时、分、秒。
（２）整点报时：逢整点蜂鸣器在“59”分钟的第51、53、55、57秒发频率为512Hz的低音，在“59”分钟的第59秒发频率为1024Hz的高音。
（３）校时：
校小时, 显示小时数码管以4Hz的频率递增计数；
校分, 显示分数码管以4Hz的频率递增计数；
校秒, 秒清0。
其他：
1．晶振为12 MHz
2. 采用CPLD 器件为ALTERA 的EPM7064SL-44
3．采用数码管显示
Multifunction digital electronic watch (1) normal time: second (60), points (60), hours (24) counts second timing frequency of 1Hz, dynamic scanning real-time display of digital works timekeeping hour, minutes and seconds. (2) The whole point timekeeping: Every whole point of the buzzer in the " 59" minutes of 51,53,55,57 second frequency is 512Hz bass made in the " 59" minutes of the first 59 seconds made the treble frequency is 1024Hz . (3) school: school hours, hours of digital tube display frequency of 4Hz counts school hours, the display of digital 4Hz for counting school, seconds cleared. Others: 1. Crystal is 12 MHz 2. Using ALTERA CPLD device as the EPM7064SL-44 3. Using digital display (2013-08-20, VHDL, 503KB, 下载3次)
多功能数字钟，具有年月日时分秒功能，同时能校时，1个八段数码管显示
Multifunctional digital clock with date, hour function, and can school, an eight digital tube display (2013-07-10, DOS, 763KB, 下载3次)
设计一台能显示时、分、秒的数字电子钟，具体要求如下：
（1）时计数器用24进制计时电路，分、秒计数器用60进制计分、计秒电路；
（2）可手动校时，能分别进行时、分的校正；
（3）能实现整点报时功能。
Design a table can display hours, minutes and seconds of digital electronic clock, the specific requirements are as follows: (a) when the counter with 24 hexadecimal timing circuits, minutes, seconds counter with 60 decimal points, namely, second circuit (2) may be Manually school, be able to separate hours, minutes correction (3) to achieve the whole point timekeeping function. (2013-06-23, VHDL, 913KB, 下载3次)
(1)设计一个具有‘时’、‘分’、‘秒’的十进制数字显示（小时从00～23）计时器。
(2)具有手动校时、校分的功能。
(3)闹钟功能，能在设定的时间发出提醒（绿色LED灯闪烁）。
(4)能进行整点报时。从59分50秒起，每隔2秒钟绿色LED灯闪一次，连续5次，达到整点时红色LED灯闪一次。
(1) design a ' when' , ' points' , ' s' decimal digital display (hour timer from 00 to 23). (2) having a manual correction, the correction sub functions. (3) The alarm clock function, can send reminders at a set time (green LED flashes). (4) The whole point timekeeping. Starting at 59 minutes and 50 seconds, every 2 seconds the green LED lights flash five times in a row, when the whole point of the red LED lights flash once. (2013-03-27, VHDL, 2KB, 下载3次)
基于VHDL基于VHDL数字电子钟设计（时、分、秒），有校时，分频，倒计时流水灯灯功能。
Based on VHDL VHDL-based design of digital electronic clock (hours, minutes, seconds), there is the school, the frequency, the countdown water lights lamp function. (2012-01-04, VHDL, 2KB, 下载3次)
满足数字钟的一切功能，包括定时，整点报时，时分秒的校时，年月的显示
Digital clock to meet all of the features, including timing, the whole point of time, when every minute of school, the years of the show (2011-12-18, VHDL, 265KB, 下载3次)
用Verilog编写的数字钟与汽车尾灯模块。其中数字钟具有时间显示的基本功能，按键校时校分，闹钟模块（包含校时校分），仿电台报时（四低一高），整点报时，12-24显示切换等强大功能。
With a digital clock in Verilog modules and automotive taillights. Digital clock which displays the basic functions of a time, school hours when school keys, alarm clock module (including school hours at school), imitation radio repeater (four low-high), the whole point timekeeping ,12-24 shows switching power. (2011-06-26, Others, 235KB, 下载3次)
基于vhdl的数字钟,分别由6个数码管显示24小时、60分钟、60秒的计数显示；设有校时、校分、秒清零校正功能，分别由3个按键控制；验证可用。
On vhdl digital clock, respectively, by 6 digital tube display 24 hours, 60 minutes, 60 seconds of the count display with school hours, school hours, seconds, cleared correction function, respectively, by three buttons control verification is available. (2009-11-13, VHDL, 261KB, 下载3次)
1.计时功能采用24小时方式，显示小时、分钟、秒。
2.采用双键校时法，MODE和SET，前者选择始终模式（包括小时、分、秒校时），后者校时脉冲。
3.结果用6个共阳数码管显示。
1. Time functions the way the 24-hour, show hours, minutes, seconds. 2. The use of double bond at the Law School, MODE and SET, always choose the former model (including the hours, minutes and seconds when the school), the latter pulse school. 3. Results A total of six positive digital display. (2009-07-27, VHDL, 318KB, 下载3次)
本程序为模拟可校时的时钟程序；clk--时钟信号,rst--清零信号,set_en--校时 使能信号,faster--快进信号,slower--快退信号,hour--小时校时,min--分钟校 时,（hh,hl,ml,mh,sh,sl）--时，分，秒显示信号。 校时的时候，秒清零。 (2008-05-02, VHDL, 110KB, 下载2次)
http://www.pudn.com/Download/item/id/450976.html
电子钟（模式转换24/12进制，校时，校分）
Clock (24/12 hex mode conversion, school hours, school hours) (2010-07-09, VHDL, 102KB, 下载2次)
简单的电子钟 实现时分秒，校时，定时，闹钟功能
Electronic clock (hour, minute, and second, the school, the timing, alarm clock) (2012-12-31, Visual C++, 341KB, 下载2次)
自己开发的电子时钟小程序，通过数码管显示时间，key1和key2控制校时校分，key3切换时钟模式和闹钟模式，切换到闹钟模式再按key1和key2即可设定闹钟时间。key4控制开启/关闭闹钟。有整点报时功能。
Self developed electronic clock applet, through the digital tube display time, key1 and key2 control time correction, Key3 switch clock mode and alarm mode, switch to the alarm mode, then press key1 and key2 can set the alarm time. Key4 controls the opening / closing of the alarm clock. There is a whole time function. (2017-12-06, Verilog, 9120KB, 下载2次)
数字时钟，实现24小时数码管显示，可以实现按键校时
Digital clock, 24 hours to achieve digital display, you can achieve the key school (2016-06-17, VHDL, 1789KB, 下载2次)
数字钟；可以实现校时、走时、单独计时以及闹钟功能。
Digital clock can be achieved when the school, while walking alone timekeeping and alarm function. (2016-05-21, VHDL, 432KB, 下载2次)
信号定义： clk： 标准时钟信号，本例中，其频率为4Hz； clk_1k： 产生闹铃音、报时音的时钟信号，本例中其频率为1024Hz； mode： 功能控制信号； 为0：计时功能； 为1：闹钟功能； 为2：手动校时功能； turn： 接按键，在手动校时功能时，选择是调整小时，还是分钟； 若长时间按住该键，还可使秒信号清零，用于精确调时； change： 接按键，手动调整时，每按一次，计数器加1； 如果长按，则连续快速加1，用于快速调时和定时； hour,min,sec：此三信号分别输出并显示时、分、秒信号， 皆采用BCD码计数，分别驱动6个数码管显示时间； alert： 输出到扬声器的信号，用于产生闹铃音和报时音； 闹铃音为持续20秒的急促的“嘀嘀嘀”音，若按住“change”键， 则可屏蔽该音；整点报时音为“嘀嘀嘀嘀—嘟”四短一长音； LD_alert： 接发光二极管，指示是否设置了闹钟功能； LD_hour： 接发光二极管，指示当前调整的是小时信号； LD_min： 接发光二极管，指示当前调整的是分钟信号。
Signal definition: clk: standard clock signal, in this case, the frequency of 4Hz clk_1k: generating an alarm sound, the sound of the chime of the clock signal, in this case a frequency of 1024Hz mode: function control signal to 0: timing functions 1: alarm clock function 2: Manual calibration function turn: take the keys, function in the manual when school choice is to adjust the hours, or minutes if long press the button, but also to second signal cleared for precise time-setting change: access key, manually adjust the time, every time you press, the counter is incremented if long press, then in quick succession by 1, when used to quickly tune and timing hour, min, sec: The three signals are output and display hours, minutes, seconds signal using BCD code are counted separately driven six digital tube display time alert: a signal output to the speaker for generating an alarm tone chime tone alarm tone sustained 20 seconds of rapid " Didi tick" sound, if the hol (2015-12-09, VHDL, 16KB, 下载2次)
数字钟的设计，系统分为5个模块，Freq_div模块，Clock_cnt模块，Clock_ctl模块，Key_ctl模块和Display模块。系统目标：用8个LED 显示时间，如9点25分10秒显示为，09－25－10。（2）设置2个按键，按键SET用于工作模式选择，按键UP用于校时。
Digital clock design, the system is divided into five modules, Freq_div module, Clock_cnt module, Clock_ctl module, Key_ctl module and Display Module. System goal: 8 LED display time as 9:25:10 displayed as ,09-25-10. (2) Set two buttons SET button for mode selection button when UP for school. (2014-03-28, Others, 1561KB, 下载2次)
数字钟，校时较分，显示,用元件例化写的vhdl文件，两个24进制，1个60进制计数器
Digital clock, when the school over the points, show cases with elements of writing vhdl file, two 24-band, a 60-ary counter (2014-03-03, VHDL, 457KB, 下载2次)