设计了一个电子时钟，功能包括定点报时，设置闹钟，校时等
Designed an electronic clock, features include fixed-point timekeeping, setting alarms, school hours, etc. (2018-07-01, Quartus II, 8987KB, 下载2次)
自己用verilog HDL写的一个数字钟模块，包括校时功能，在Maxplusii下调试和下载通过
A digital clock module written by Verilog HDL, including timing function, debugging and downloading through Maxplusii. (2018-04-13, Verilog, 3KB, 下载2次)
多功能数字种 可实现校时 闹钟 整点报时等功能
Multi-function digital species can realize the function of time alarm clock and other functions (2018-02-10, Verilog, 2KB, 下载2次)
基于verilog简单数字时钟程序，可实现校时，校分功能
Based verilog simple digital clock procedures, can be achieved when the school, school division function (2016-07-03, VHDL, 1128KB, 下载1次)
显示时、分、秒，有手动校时功能，计时过程具有报时功能
Display hours, minutes, seconds, manual timing function, timing processes with chime (2016-03-26, VHDL, 13KB, 下载1次)
数字电子钟的设计，振荡器产生稳定的高频脉冲信号,作为数字钟的时间基准,然后经过分频器输出标准秒脉冲。秒计数器满60后向分计数器进位,分计数器满60后向小时计数器进位,小时计数器按照“24翻1”规律计数。计数器的输出分别经译码器送显示器显示。计时出现误差时,可以用校时电路校时、校分。
Digital electronic clock design, stable high frequency oscillator generates a pulse signal as a digital clock time reference, and then passes through a divider output standard second pulse. Second counter at least 60 minutes after the binary counter, minute counter at least 60 hours after the binary counter, hour counter in accordance with the "24 turn a" regular count. The outputs of the counter is sent to the decoded display. Timing errors, you can use the circuit when the school when the school, school hours.
(2013-07-02, VHDL, 1469KB, 下载1次)
12制 24制可切换电子钟，有时分秒，都可校时
clock can adjust minute,hour,seconds (2018-05-11, Verilog, 747KB, 下载1次)
程序是实现一个数字钟，有进位、清零、校时与校分功能。数字钟的分钟和小时是用数码管显示
COUNTER AND ALARMProblem C. Cave Escape Google Kickstart Round G 2018 [Small Input] (2019-04-26, Verilog, 1599KB, 下载1次)
合肥工业大学合肥校区(HFUT)计算机科学与技术专业(CS)。本仓库存有大一至大三的实验+课设及其源码,有疑问可以邮箱联系(回复时间不一定)。欢迎Star,会不定时更新
Computer Science and Technology (CS) at Hefei Campus of Hefei University of Technology (HFUT). This warehouse has the experiment+curriculum and its source code from freshman to junior. If you have any questions, you can contact us by email (the reply time is uncertain). Welcome Star, it will be updated irregularly (2024-01-21, Rich Text Format, 0KB, 下载0次)
UFSC语言和硬件描述课程知识库，Araranguá校区。，
Repository for the Language and Hardware Description course at UFSC, Araranguá campus., (2023-03-02, VHDL, 0KB, 下载0次)
实现计时，置数，闹钟设置，切换显示等
1.硬件资源：FPGA开发板一块，电源线一根，下载器一个
2.开发板用到的资源：三颗独立按键，一位拨码开关，八位七段数码显示器，
蜂鸣器
3.功能设计：时钟功能，校时功能，闹钟功能
整个系统分为7大模块
Realize timing, setting, alarm setting, switching display, etc
1. Hardware resources: one FPGA development board, one power cord and one Downloader
2. Resources used in the development board: three independent buttons, one dial switch, eight seven segment digital display,
Buzzer
3. Function design: clock function, timing function, alarm function
The whole system is divided into seven modules (2020-06-16, Verilog, 2381KB, 下载0次)