UFSC语言和硬件描述课程知识库，Araranguá校区。，
Repository for the Language and Hardware Description course at UFSC, Araranguá campus., (2023-03-02, VHDL, 0KB, 下载0次)
数字时钟，实现24小时数码管显示，可以实现按键校时
Digital clock, 24 hours to achieve digital display, you can achieve the key school (2016-06-17, VHDL, 1789KB, 下载2次)
数字钟；可以实现校时、走时、单独计时以及闹钟功能。
Digital clock can be achieved when the school, while walking alone timekeeping and alarm function. (2016-05-21, VHDL, 432KB, 下载2次)
基于fpga的多功能数字时钟 在数码管显示
verilog语言编写 可实现校时 暂停以及设定闹钟的功能
FPGA time clock (2015-05-02, VHDL, 74KB, 下载4次)
verilog电子时钟，可以实现复位、计时、校时、闹钟等多种功能。
verilog electronic clock, you can achieve a variety of functions reset, time, school, alarm clock and so on. (2013-12-12, VHDL, 363KB, 下载5次)
设计一个多功能数字时钟:时钟显示，手动校时，整点报时，闹钟功能
Clock manually school, the whole point timekeeping, alarm clock function (2013-04-09, VHDL, 360KB, 下载8次)
多功能时钟，具有正常显示，校时，整点报时，闹钟功能。
Multi-function clock, with a normal school, the whole point timekeeping, alarm clock function. (2012-11-26, VHDL, 470KB, 下载5次)
基于UP3borad开发板的时钟设计，可校时，设置闹钟等
Clock design based on UP3borad the development board, can the school, set the alarm (2012-05-23, VHDL, 354KB, 下载6次)
数字时钟，整点报时，有校分校时功能，底层用VHDL，顶层原理图
Digital clock, the whole point of time, when a school campus functions, the bottom with VHDL, top-level schematic (2012-01-05, VHDL, 4KB, 下载4次)
电子表的设计,包括正常计时模块，LED显示模块，定时报警模块，校时模块，秒表模块。
Electronic form design, including the normal timing module, LED display module, timing alarm module, timing modules, stopwatch modules. (2011-12-14, VHDL, 2KB, 下载7次)
用Verilog HDL 设计一个多功能数字钟，包含以下主要功能：
（1） 计时，时间以24小时制显示。
（2） 校时，
（3） 跑表：启动、停止、暂停
Verilog HDL design with a multi-functional digital clock, includes the following main functions: (1) time, time to 24-hour display. (2) school, (3) stopwatch: start, stop, pause (2010-12-02, VHDL, 1342KB, 下载7次)
基于CPLD的交通灯控制，完成交通灯的功能，校错能力
CPLD-based control of traffic lights, traffic lights to complete the function, the school was wrong capacity (2010-10-08, VHDL, 426KB, 下载5次)
数字钟，用VHDL 编写。具有计时，校时（调分调时），报时功能
Digital clock, written with VHDL. With time, school time (when the tone on tones), timekeeping function (2010-09-02, VHDL, 188KB, 下载5次)
闹钟、电子钟典型实例，具有校时，整点报时等功能
Alarm clock, electronic clock typical example, a school, the whole point of time and other functions (2010-04-25, VHDL, 245KB, 下载7次)
多功能数字时钟课程设计可用的,含手动校时电路，整点报时电路。报时长短需要自己设置程序
digital clock decode (2010-04-24, VHDL, 1KB, 下载9次)
这是一个基于FPGA设计的24时多功能数字钟，具有正常星期、时、分、秒计时，动态显示，保持、清零、快速校分、整点报时、闹钟功能。
This is an FPGA-based design of multi-function digital clock 24 hours, with a normal week, hours, minutes, seconds, timing, dynamic display, maintaining, resetting, fast school hours, the whole point timekeeping, alarm clock function. (2010-03-06, VHDL, 773KB, 下载27次)
s1. 所设计数字钟具有“时”、“分”、“秒”的十进制数字显示（小时从00～23）。
2. 可以进行手动校时、校分功能。
3. 能进行整点报时。从59分51秒开始每隔2秒钟连续发出四次低音“嘟。嘟、嘟、嘟”，，最后一次发出高音“嗒”。此信号响起时即达整点。
you can see see (2009-12-03, VHDL, 157KB, 下载24次)
基于vhdl的数字钟,分别由6个数码管显示24小时、60分钟、60秒的计数显示；设有校时、校分、秒清零校正功能，分别由3个按键控制；验证可用。
On vhdl digital clock, respectively, by 6 digital tube display 24 hours, 60 minutes, 60 seconds of the count display with school hours, school hours, seconds, cleared correction function, respectively, by three buttons control verification is available. (2009-11-13, VHDL, 261KB, 下载3次)
这时一个关于数字钟的VHDL程序，有计时、校时、报时等功能
When a digital clock on the VHDL program, there is time, school time, timer and other functions (2009-09-22, VHDL, 79KB, 下载6次)
用VHDL语言编写的一个乘法器校程序
是基于BOOTH算法的
VHDL language using a multiplier BOOTH school program is based on the algorithm (2008-05-22, VHDL, 1KB, 下载25次)