基于VHDL的数字时钟课程设计，可实现校时、计时已经闹钟功能。
The course design of digital clock based on VHDL can realize the alarm clock function of school hour and time. (2018-12-25, VHDL, 186KB, 下载5次)
数字钟，校时较分，显示,用元件例化写的vhdl文件，两个24进制，1个60进制计数器
Digital clock, when the school over the points, show cases with elements of writing vhdl file, two 24-band, a 60-ary counter (2014-03-03, VHDL, 457KB, 下载2次)
数字钟，实现整点报时以及校时功能，烟大数字逻辑课程实验。
Digital clock, realize the whole point timekeeping and school function, smoke large digital logic course experiment. (2013-11-08, VHDL, 496KB, 下载3次)
数字钟，功能：12时/24时切换显示，校时,时间很准（4位数码管显示），内含sof，pof，tcl，四个文件，在开发板C1上已实现
digital clock ，verilog (2013-08-21, VHDL, 18KB, 下载7次)
多功能数字电子表
（１）正常计时：秒（60）、分（60）、小时（24）计数；秒计时的频率为1Hz，数码管用动态扫描实时显示计时的小时、分、秒。
（２）整点报时：逢整点蜂鸣器在“59”分钟的第51、53、55、57秒发频率为512Hz的低音，在“59”分钟的第59秒发频率为1024Hz的高音。
（３）校时：
校小时, 显示小时数码管以4Hz的频率递增计数；
校分, 显示分数码管以4Hz的频率递增计数；
校秒, 秒清0。
其他：
1．晶振为12 MHz
2. 采用CPLD 器件为ALTERA 的EPM7064SL-44
3．采用数码管显示
Multifunction digital electronic watch (1) normal time: second (60), points (60), hours (24) counts second timing frequency of 1Hz, dynamic scanning real-time display of digital works timekeeping hour, minutes and seconds. (2) The whole point timekeeping: Every whole point of the buzzer in the " 59" minutes of 51,53,55,57 second frequency is 512Hz bass made in the " 59" minutes of the first 59 seconds made the treble frequency is 1024Hz . (3) school: school hours, hours of digital tube display frequency of 4Hz counts school hours, the display of digital 4Hz for counting school, seconds cleared. Others: 1. Crystal is 12 MHz 2. Using ALTERA CPLD device as the EPM7064SL-44 3. Using digital display (2013-08-20, VHDL, 503KB, 下载3次)
数字电子钟的设计，振荡器产生稳定的高频脉冲信号,作为数字钟的时间基准,然后经过分频器输出标准秒脉冲。秒计数器满60后向分计数器进位,分计数器满60后向小时计数器进位,小时计数器按照“24翻1”规律计数。计数器的输出分别经译码器送显示器显示。计时出现误差时,可以用校时电路校时、校分。
Digital electronic clock design, stable high frequency oscillator generates a pulse signal as a digital clock time reference, and then passes through a divider output standard second pulse. Second counter at least 60 minutes after the binary counter, minute counter at least 60 hours after the binary counter, hour counter in accordance with the "24 turn a" regular count. The outputs of the counter is sent to the decoded display. Timing errors, you can use the circuit when the school when the school, school hours.
(2013-07-02, VHDL, 1469KB, 下载1次)
数字钟verilog程序，实现了校时、闹钟校正、整点报时、当前时间与闹钟时间切换显示功能。
Digital clock verilog program, school, alarm clock correction, the whole point timekeeping function. (2012-12-15, VHDL, 100KB, 下载10次)
电子表的设计包括正常计时模块，LED显示模块，定时报警模块，校时模块，秒表模块
module clock(clk,rst,clock_en,second,minute,hour)
input clk,rst,clock_en
output[5:0]second,minute,hour
reg[5:0]second,minute,hour
(2012-06-19, VHDL, 109KB, 下载3次)
多功能数字钟 24小时计时 整点报时功能 闹钟设置功能 校时 复位等
Multi-function digital clock 24 hours to strike the alarm clock on the hour function when the reset function, etc (2012-01-05, VHDL, 11KB, 下载7次)
满足数字钟的一切功能，包括定时，整点报时，时分秒的校时，年月的显示
Digital clock to meet all of the features, including timing, the whole point of time, when every minute of school, the years of the show (2011-12-18, VHDL, 265KB, 下载3次)
多功能数字钟，实现了计时、校分、闹钟、日历等功能，已通过仿真验证
Multifunction digital clock, to achieve the timing, the school points, alarm clock, calendar and other functions, has been verified by simulation (2011-09-23, VHDL, 1251KB, 下载10次)
用VHDL编写。数字钟校时电路，根据表示是否校时的输入引脚、是校正小时还是校正分钟的输入引脚决定校正状态。接受一个按钮的脉冲输入，每输入一个脉冲，被校正的时间增加1.与我的其它8个模块配套构成一个数字钟。
Programmed with VHDL.The time-revising circuit of a digital clock. Detect the inputs and decide if revise time, hour or minute. It recepts an impulse input from a key and the currently revised time will increase by 1 for each pushing of the key. (2011-06-24, VHDL, 116KB, 下载4次)
数字钟的实现，包括报时，校时，清零，闹钟等功能，内附源文件电路图跟源代码。
This is a digital clock to achieve the VHDL. Using eight digital tube display!- Adjustable alarm can be school. (2011-06-15, VHDL, 90KB, 下载4次)
利用QuartusII7.0、MATLAB以及SmartSOPC实验系统进行多功能数字钟的设计是本次试验的主要内容。该数字中需包含的功能主要有：分频、校时校分、清零、动态显示、整点报时、闹钟闹铃、秒表以及24小时制和12小时制的转换等。
QuartusII7.0, MATLAB, and SmartSOPC experimental system for the design of multi-function digital clock is the main content of the trial. The figure is included in the functions needed are: sub-band, school, when school hours, resetting, dynamic display, the whole point timekeeping, alarm clock alarm, stopwatch and 24-hour system and 12-hour system conversion. (2011-06-08, VHDL, 249KB, 下载9次)
可实现校时，仿电台报时，闹钟，报整点时数
The school can be realized when the fake radio timekeeping, alarm clock, reported that the number of hours the whole point of (2009-12-30, VHDL, 13KB, 下载18次)
1、24小时计数显示；
2、具有校时功能（时，分） ；
3、实现闹钟功能（定时，闹响）；
1,24 hours counting display 2, with the school when the function (hour, minute) 3 to achieve alarm functions (timing, downtown ring) (2009-12-01, VHDL, 7KB, 下载4次)
这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用
When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design (2009-09-22, VHDL, 1KB, 下载7次)
用VHDL实现的完整数字钟代码，时分秒计时、校时、整点仿电台报时。
Used to achieve a complete VHDL code digital clock, accurate time at school, the whole point of imitation time radio. (2009-05-21, VHDL, 288KB, 下载5次)
VHDL的数字时钟程序
24小时计数显示；
具有校时功能（时，分） ；
实现闹钟功能（定时，闹响）；
VHDL digital clock counting procedures showed that 24 hours with a school function (hours, minutes) the realization of an alarm clock function (timing, downtown ring) (2009-01-08, VHDL, 12KB, 下载6次)
基于bcd码校时的数字钟，带闹钟，正点报时，和日历功能
Price coverlet bcd tungsten cavity时corchorifolius tub callous钟turbulent age钟， ， ，时forlorn Hao Yu Rui Kun Dang 日 Xikui (2008-07-11, VHDL, 2KB, 下载29次)