基于FPGA的数字万年历设计。可显示年月日时分秒星期，可校时，可整点报时。
FPGA-based design of digital calendar. Displays the date when the minutes and seconds the week, when the school can be the whole point timekeeping. (2016-06-27, VHDL, 150KB, 下载8次)
该程序主要是用Verilog HDL语言编写的多功能数字钟，包括校时，调试，整点报时和万年历模块。
The program is mainly used Verilog HDL language multifunction digital clock, including at school, debugging, the whole point timekeeping and calendar modules. (2016-05-14, VHDL, 9KB, 下载5次)
采用可综合的Verilog代码编写一个带闹钟功能的数字钟。使其具有以下功能：
1)计时功能：包括小时、分钟、秒钟。
2)校时功能：对小时、分钟和秒钟进行手动校时。
3)定时和闹钟功能：能在手工设定的时间产生闹铃音。
Using synthesizable Verilog coding a digital clock with alarm. It has the following features:
1) timing functions include: hours, minutes, seconds.
2) When the school functions: hours, minutes and seconds to the manual correction.
3) timing and alarm functions: to produce an alarm sound at the set time manually. (2015-01-24, VHDL, 2KB, 下载8次)
这个程序是基于Quartus II的，能通过数码管显示时、分、秒，具有闹钟的功能，能通过按键校时。
his program is based on the Quartus II, and when through digital display hours, minutes, seconds, and has an alarm clock function, button through school. (2014-11-30, VHDL, 1KB, 下载4次)
本设计选用 ALTERA 公司的 EP1C12Q240C8 芯片，利用 VHDL 语言采用自
顶向下的方法在 Quartus Ⅱ环境下完成了数字钟的设计，最后在实验箱上进行测
试。该数字钟包含的功能有计时、显示星期、校时校分、清零、整点报时、音乐
闹铃。
The design uses the silicon chip EP1C12Q240C8 produced by the company of
ALTERA. And with the help of VHDL, the design of a digital clock is completed
using the top-down approach under Quartus Ⅱ, finally carried out in the SmartSOPC.
Functions of the digital clock are: timer, showing day, setting time, resetting, Chime
on every hour, and alarm with music. (2014-05-20, VHDL, 226KB, 下载4次)
电子时钟设计 包含校时和闹钟功能 闹钟播放一段音乐 ppt和word报告也有 太大不上传 需要的发邮箱lin170587788@gmail.com
Electronic clock and alarm functions including school play a musical alarm clock ppt and word report also does not upload much needed hair mailbox lin170587788@gmail.com (2013-06-17, VHDL, 315KB, 下载4次)
(1)设计一个具有‘时’、‘分’、‘秒’的十进制数字显示（小时从00～23）计时器。
(2)具有手动校时、校分的功能。
(3)闹钟功能，能在设定的时间发出提醒（绿色LED灯闪烁）。
(4)能进行整点报时。从59分50秒起，每隔2秒钟绿色LED灯闪一次，连续5次，达到整点时红色LED灯闪一次。
(1) design a ' when' , ' points' , ' s' decimal digital display (hour timer from 00 to 23). (2) having a manual correction, the correction sub functions. (3) The alarm clock function, can send reminders at a set time (green LED flashes). (4) The whole point timekeeping. Starting at 59 minutes and 50 seconds, every 2 seconds the green LED lights flash five times in a row, when the whole point of the red LED lights flash once. (2013-03-27, VHDL, 2KB, 下载3次)
多功能数字钟 24小时计时 整点报时功能 闹钟设置功能 校时 复位等
Multi-function digital clock 24 hours to strike the alarm clock on the hour function when the reset function, etc (2012-01-05, VHDL, 2KB, 下载6次)
基于VHDL基于VHDL数字电子钟设计（时、分、秒），有校时，分频，倒计时流水灯灯功能。
Based on VHDL VHDL-based design of digital electronic clock (hours, minutes, seconds), there is the school, the frequency, the countdown water lights lamp function. (2012-01-04, VHDL, 2KB, 下载3次)
电子数字钟，周期为24小时，显示满刻度为23时59分59秒，另外还具有校时功能和闹钟功能
Electronic digital clock, 24-hour period, indicating full scale as 23:59:59, when the school also has a function and alarm functions (2011-05-24, VHDL, 44KB, 下载6次)
1) 计时计数器用24进制计时器电路。
2) 可手动校时，能清零及分别进行时、分、秒的校正。
3) 可整点报时，扬声器发出时长为1s的信号。
4) 可设置闹钟功能。当计时计到预定时间时，扬声器发出闹铃信号，可控制闹铃时长。
clock (2010-12-17, VHDL, 844KB, 下载5次)
数字钟的VHDL语言实现基本功能，包括
1、24小时计数显示；
2、具有校时功能（时，分） ；
附加要求：
1、实现闹钟功能（定时，闹响）；
Digital clock in the VHDL language for basic functions, including 1,24-hour count display 2, when a school function (hour, minute) additional requirements: 1, to achieve the alarm function (time, alarm sound) (2010-11-25, VHDL, 1KB, 下载3次)
本文介绍了一个多功能电子钟的设计方案。该方案具有计时、整点报时、校时、校分、闹钟等多项功能。此方案基于Altera 公司的 Cyclone 芯片及Quartus II 7.2 软件。整体设计采用自顶向下的设计思想，大量使用了器件模块化操作。本文对于研究数字钟及扩大其应用，有着非常现实的意义。
This paper describes a multi-clock design. The program has the time, the whole point of time, school hours, school hours, alarm clocks and many other features. This program is based on Altera' s Cyclone chip and Quartus II 7.2 software. The overall design using top-down design, extensive use of modular operation of the device. This digital clock for research and expand its application, has a very practical significance. (2010-09-08, VHDL, 756KB, 下载12次)
VHDL数字钟设计程序 设计要求 基本要求： 1、24小时计数显示； 2、具有校时功能（时，分） ； 附加要求： 1、实现闹钟功能（定时，闹响）；-
VHDL design process digital clock design basic requirements: 1.24 hours count display 2, when a school function (hour, minute) additional requirements: 1, to achieve alarm (time, alarm sound) - (2010-06-22, VHDL, 70KB, 下载48次)
实验利借助于Quartus II 软件设计了一个多功能数字钟，实现了校时，校分，清零，保持和整点报时等多种基本功能，此外还实现了闹钟，星期，音乐闹铃等附加功能。本文首先利用Quartus II进行原理图设计并仿真调试，最后在实验板上验证了设计的正确性。
关键字：数字钟 闹钟 仿真 准点报时
Quartus II software by means of experimental Lee designed a multi-functional digital clock and realized the school, the school hours, cleared, and the whole point of time keeping and other basic functions, in addition to achieve the alarm clock, week, music, alarm, etc. Additional function. This paper carried out using Quartus II schematic design and simulation debugging, and finally verified in the experimental board design is correct. Keywords: digital clock alarm clock simulation of quasi-point of time (2010-05-08, VHDL, 1158KB, 下载13次)
eda实验时钟电路系统由秒时钟产生电路、走时电路模块、数字显示模块、校时模块、语音报时模块、工业控制模块
eda test clock circuit generated by the second clock circuit, the circuit blocks away, the digital display module, the campus module, voice timekeeping module, industrial control modules (2010-04-18, VHDL, 2578KB, 下载27次)
以前学习VHDL语言时做的一个电子闹钟程序，可以实现时，分，秒的计时以及定时，校时，闹钟，整点报时的功能。
VHDL language before learning to do procedures in an electronic alarm clock, you can realize hours, minutes and seconds of time and from time to time, school time, alarm clock, the whole point timekeeping function. (2008-09-25, VHDL, 166KB, 下载13次)
电子时钟 EDA
基本要求：
24小时计数显示；
具有校时功能（时，分）
附加要求
1、秒表功能（复位，计时
Electronic clock EDA basic requirements: a 24-hour count showed with a school function (hours, minutes,) Additional requirement 1, stopwatch functions (reset, clock (2008-09-18, VHDL, 3KB, 下载33次)
ADC0809采样控制电路的实现ADC0809是CMOS的8位A/D转换器，片内有8路模拟开关，可控制8个模拟量中的一个进入转换器中，转换时间约100us。主要控制信号有，START是转换启动信号，高电平有效。ALE是3位通道选择地址（ADDC、ADDB、ADDA）信号的所存信号。当模拟量送至某一输入端（如IN1或IN2），由3位地址信号选择，而地址信号由ALE锁存。
ADC0809频 实 ADC0809CMOS8位A/D 转 片8 模 饪?兀 煽8模 械一 转 校 转 时 约 100us要藕校START 转 藕牛 叩 平效ALE3位 通 选ADDCADDBADDA藕诺藕拧模 某一 耍 IN1IN23位藕选 瘢 藕ALE file (2008-09-04, VHDL, 28KB, 下载38次)
这是一个数字钟的VHDL实现.采用八段数码管显示！
--可调闹铃，可校时。
This is a digital clock to achieve the VHDL. Using eight digital tube display!- Adjustable alarm can be school. (2008-06-26, VHDL, 5KB, 下载68次)