信号定义： clk： 标准时钟信号，本例中，其频率为4Hz； clk_1k： 产生闹铃音、报时音的时钟信号，本例中其频率为1024Hz； mode： 功能控制信号； 为0：计时功能； 为1：闹钟功能； 为2：手动校时功能； turn： 接按键，在手动校时功能时，选择是调整小时，还是分钟； 若长时间按住该键，还可使秒信号清零，用于精确调时； change： 接按键，手动调整时，每按一次，计数器加1； 如果长按，则连续快速加1，用于快速调时和定时； hour,min,sec：此三信号分别输出并显示时、分、秒信号， 皆采用BCD码计数，分别驱动6个数码管显示时间； alert： 输出到扬声器的信号，用于产生闹铃音和报时音； 闹铃音为持续20秒的急促的“嘀嘀嘀”音，若按住“change”键， 则可屏蔽该音；整点报时音为“嘀嘀嘀嘀—嘟”四短一长音； LD_alert： 接发光二极管，指示是否设置了闹钟功能； LD_hour： 接发光二极管，指示当前调整的是小时信号； LD_min： 接发光二极管，指示当前调整的是分钟信号。
Signal definition: clk: standard clock signal, in this case, the frequency of 4Hz clk_1k: generating an alarm sound, the sound of the chime of the clock signal, in this case a frequency of 1024Hz mode: function control signal to 0: timing functions 1: alarm clock function 2: Manual calibration function turn: take the keys, function in the manual when school choice is to adjust the hours, or minutes if long press the button, but also to second signal cleared for precise time-setting change: access key, manually adjust the time, every time you press, the counter is incremented if long press, then in quick succession by 1, when used to quickly tune and timing hour, min, sec: The three signals are output and display hours, minutes, seconds signal using BCD code are counted separately driven six digital tube display time alert: a signal output to the speaker for generating an alarm tone chime tone alarm tone sustained 20 seconds of rapid " Didi tick" sound, if the hol (2015-12-09, VHDL, 16KB, 下载2次)
基于QuartusII开发环境，Cyclone III开发板的VerilogHDL多功能数字钟程序。可实现24小时计时，手动校时，闹钟，整点报时功能。分频模块在仿真和烧写是需要改变。
QuartusII based development environment, Cyclone III development board VerilogHDL multifunction digital clock procedures. Can achieve 24-hour clock, manual timing, alarm, hourly chime functions. Frequency module in the simulation and programming needs to change. (2013-07-24, VHDL, 1895KB, 下载4次)
设计一台能显示时、分、秒的数字电子钟，具体要求如下：
（1）时计数器用24进制计时电路，分、秒计数器用60进制计分、计秒电路；
（2）可手动校时，能分别进行时、分的校正；
（3）能实现整点报时功能。
Design a table can display hours, minutes and seconds of digital electronic clock, the specific requirements are as follows: (a) when the counter with 24 hexadecimal timing circuits, minutes, seconds counter with 60 decimal points, namely, second circuit (2) may be Manually school, be able to separate hours, minutes correction (3) to achieve the whole point timekeeping function. (2013-06-23, VHDL, 913KB, 下载3次)
用 Verilog HDL 设计一个多功能数字钟，包含以下主要功能：
1） 计时，时间以 24 小时制显示；
2） 校时；
3） 闹钟：设定闹钟时间，可利用 LED 闪烁作为闹钟提示；
4） 跑表：启动、停止；
5） 其他。
Using Verilog HDL design a multi-functional digital clock contains the following main functions: 1) time, the time is displayed in 24-hour clock 2) school 3) Alarm Clock: Set the alarm time, you can use the LED flashes as an alarm 4) Stopwatch: start, stop 5) Other. (2013-04-24, VHDL, 1206KB, 下载33次)
数字钟(for DE2 开发板)
1.‘时’、‘分’、‘秒’的十进制数字显示（小时从00～23）计时器。
2. 手动校时、校分、校秒的功能。
3．定时与闹钟功能，能在设定的时间发出闹铃声。
4．进行整点报时。从59分50秒起，每隔2秒钟发出一次低音“嘟”的信号，连续5次，最后一次发出高音“嘀”的信号，此信号结束即达到整点。
5、一个秒表，最低位1 秒、60秒，手动停止，手动重置。
6、一个倒计时，显示小时、分钟、秒，可设置时间。
Decimal digital display (hour digital clock (for DE2 development board). ' ' , ' Minutes' , ' seconds' timer from 00 to 23). 2 when manually school, the school points School sec functionality. 3. Timer and alarm clock function, the alarm sounds at the set time. 4. The whole point of time. Starting at 59 minutes and 50 seconds, every 2 seconds issued time bass " beep" signal, five times in a row, the last issued a the treble " tick" signal, this signal the end to reach the whole point. 5, a stopwatch, the lowest 1 seconds, 60 seconds, manually stop manually reset. 6, a countdown display hours, minutes, seconds, set the time. (2012-11-11, VHDL, 887KB, 下载77次)
本数字钟可实现正常计时，支持12小时和24小时两种计时方式的切换，允许用户手动调时和整点报时功能。
系统对外向用户提供了两个按键:功能键和调整键.功能键用于功能选择,调整键用于相关的时间调整. 当接通电源后系统便开始正常计时，如果按一下功能键，则进入调小时模式,再按一次则进入调分模式,再按则进入12/24小时模式选择设定,再按则恢复到正常计时状态. 在正常计时状态下，用户可以选择12或24小时的计时方式，第六个数码管的右下方小点亮表示是12小时模式，不亮表示24小时。整点报时时，六个数码管的小点会同时亮。
当用户通过按键进入校时状态时，第二个数码管的小点变亮，表示现在在对小时进行设置；同样，进行校分状态时，第四个数码管的小点会亮，表示现在正在对分钟进行设置。
The digital clock can achieve normal timing, support for 12 hours and 24 hours two timing mode switch allows the user to manually tune and the whole hour. Systems external to provide users with two keys: the function key and adjust the key function keys for function selection and adjustment button for the relevant time to adjust the power system began timing, if you click a function key, adjust the hour mode, and then once for the tone patterns, and then enter 12/24 hour mode select Settings, and then restored to normal timekeeping. in normal time status, the user can select 12 or 24 hours timing sixth of the way, the bottom right of the small digital tube light 12 hour mode, light 24 hours. The whole point of time when the dot of six digital tube light. Button to enter the school when the second digital tube light, that now the hour set Similarly, when the school sub-state, the fourth digital control points will be bright, said that now are minute set. (2012-05-25, VHDL, 17KB, 下载3次)
本设计主要研究基于FPGA的数字钟，要求时间以24小时为一个周期,显示年、月、日、时、分、秒。具有校时以及报时功能，可以对年、月、日、时、分及秒进行单独校对，使其校正到标准时间。
This design is the main research based on FPGA digital clock, required time to 24 hours for a cycle, display date and time, minutes and seconds. The strike has and function, can to year, month, day, and minutes and seconds to the separate proofreading (2012-03-18, VHDL, 157KB, 下载4次)
此数字钟具有时，分，秒计时并显示功能；
2.能进行24/12小时制计时模块的切换；
3.具有校时，清除功能，能对时，分，秒进行调整；
4.具有整点报时功能：在59分51秒，59分53秒，59分55秒，59分57秒发出低音256HZ信号，在59分59秒发出一次高音1024HZ信号，音响持续一秒钟，在1024HZ音响结束时刻即为整点；
This digital clock with hours, minutes, seconds, chronograph and display 2 24/12 hour time capable of switching modules 3 with the school, clean up, can the hours, minutes, seconds to adjust 4 with The whole point timekeeping functions: in 59 minutes and 51 seconds, 59 minutes and 53 seconds, 59 minutes and 55 seconds, 59 minutes and 57 seconds bass 256HZ signal sent in 59 minutes and 59 seconds to issue a treble 1024HZ signals, sound for one second, sound in 1024HZ end time is the whole point (2011-11-13, VHDL, 703KB, 下载4次)
1.计时功能：包括时、分、秒的计时
2.定时与闹钟功能：能在设定的时间按发出闹铃声
3.校时功能：对小时、分钟和秒能手动调整以校准时间
4.整点报时功能
5.利用数码管显示时间
1. The timer function: including, minutes and seconds when the timing
2. The timing and alarm clock function: set time out according to the alarm
3. When the function of hours, minutes and: can manual adjustments to calibration second time
4. Strike on the function
5. Using digital pipe display time (2011-07-29, VHDL, 2KB, 下载4次)
用VHDL编写。称为校时闪烁电路。一般的电子表在校时时都会使被校正的时间不停地闪烁。此模块实现了类似的功能。与我的其它8个模块配套构成一个数字钟。
Programmed with VHDL. It is called a flashing circuit(when time is being revised).Generally, a digital watch will flash the currently revised time(for example,hour) to let the user know time revised. This module implements the similar function. It is one of my total 9 modules that are used to design a digital clock. (2011-06-24, VHDL, 140KB, 下载4次)
电子钟的设计，(1) 计时功能：这是本计时器设计的基本功能，可进行时、分、秒计时，并显示。
(2) 闹钟功能：如果当前时间与设置的闹钟时间相同，则扬声器发出一段音乐，并维持一分钟。
(3) 调时调分调闹钟功能：当需要校时或者要重新设置闹钟的时间时，可通过实验箱上的按键控制。
The design of electronic clock, (1) timer function: This is the basic design of the timer function, can be hours, minutes, seconds, time, and displayed. (2) Alarm function: If the current time and set the alarm clock the same time, the speaker issued a piece of music, and to maintain a minute. (3) adjusting the tone when the tone alarm sub-functions: the school or when when you need to re-set the alarm time, the experimental box through the keys on the control. (2010-11-30, VHDL, 82KB, 下载7次)
VerilogHDL编译基本功能具有“秒”、“分”、“时”计时功能，小时按24小时制计时。具有校时功能，能对“分”和“小时”进行调整。扩展功能
仿广播电台正点报时。在59分51秒、53秒、55秒、57秒发出低音512Hz信号，在59分59秒时发出一次高音1024Hz信号，音响持续1秒钟，在1024Hz音响结束时刻为整点。
定时控制，其时间自定；
可任意设定时间的闹钟
自动报整点小时数
小时显示：可切换12小时/24小时显示
VerilogHDL compile the basic functions of a " second" , " division" and " when" time function, hour by 24-hour time. When a school function, can " divide" and " hours" to adjust. Radio extension punctual timekeeping imitation. In 59 minutes and 51 seconds, 53 seconds, 55 seconds, 57 seconds sent the bass 512Hz signal, in 59 minutes and 59 seconds to issue a Treble 1024Hz signal, sound for 1 second, the end of the 1024Hz sound time for the whole point. Timing control, its time to custom can be arbitrarily set the time automatically report the whole point of the alarm clock an hour for several hours show: switchable 12 hours/24 hours display (2010-06-20, VHDL, 1KB, 下载5次)
基于FPGA的数字电子钟设计，系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时，显示满刻度为23时59分59秒，另外有校时、校分和整点报时功能，并通过数码管驱动电路显示计时结果。
FPGA-based design of digital electronic clock, the system program by the total frequency module, " the minutes and seconds" counter module, data selection module, timer module, dynamic scanning display and decoding module. Get a will " ," and " division" and " seconds" display on the human visual organ of the timing device. It' s time for the 24-hour period, indicating full scale as 23:59:59, and another school, the school hours and the whole hour, and through digital tube display driver circuit timing results. (2010-04-07, VHDL, 62KB, 下载27次)
VHDL数字钟设计程序
设计要求
基本要求：
1、24小时计数显示；
2、具有校时功能（时，分） ；
附加要求：
1、实现闹钟功能（定时，闹响）；
VHDL digital clock design process design requirements for the basic requirements: 1,24 hours count display 2, with a school function (hours, minutes) additional requirements: 1, the realization of an alarm clock function (timing, downtown ring) (2008-12-23, VHDL, 7KB, 下载129次)
学习使用FPGA做一些简单的编码器,RS(5,3)编码就是5个字符中有5-3=2两个校正字
Learning to use the FPGA to do a few simple encoders, RS (5,3) code is five characters in 5-3 = 2 has two correction words (2008-04-01, VHDL, 969KB, 下载136次)