中值滤波的实现，该代码使用的是verilog 语言
module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)
Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1, b1, c1) (2009-11-04, VHDL, 2KB, 下载114次)