这是WHU武汉大学2023-2024学年 计卓班 计算机组成与设计 RISC-V CPU 流水线设计，包括Modelsim仿真测试，vivado下FPGA(NEXYS A7)测试。, stars:1, update:2024-05-15 14:42:05 (2024-05-16, Verilog, 0KB, 下载0次)
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RISC-V 5级流水线RV32I实现，在verilog中转发，具有在xilinx nexus a7 FPGA上工作的驱动程序...
RISC-V 5-stage pipeline RV32I implementation with forwarding in verilog with drivers to work on xilinx nexus a7 FPGA boards (2022-08-22, Verilog, 1156KB, 下载0次)