DW 256 DUP(?)
STACK1 ENDS
DDATA SEGMENT
MES1 DB The least number is:$
MES2 DB 0AH,0DH, The largest number is:$
NUMB DB 0D9H,07H,8BH,0C5H,0EBH,04H,9DH,0F9H
DDATA ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DDATA
START: MOV AX,DDATA
MOV DS,AX
MOV SI,OFFSET NUMB
MOV CX,0008H
JCXZ A4
MOV BH,[SI]
MOV BL,BH
A1: LODSB AL=DS:[SI],SI=SI+1
CMP AL,BH
JBE A2
MOV BH,AL
JMP A3
A2: CMP AL,BL
JAE A3
MOV BL,AL
A3: LOOP A1
A4: MOV DX,OFFSET MES1 show mes1
MOV AH,09H
INT 21H
MOV AL,BL show the least number
AND AL,0F0H get the highest 4 bits
SHR AL,4
CMP AL,0AH
JB C2
ADD AL,07H
C2: ADD AL,30H
MOV DL,AL show character
MOV AH,02H
INT 21H
MOV AL,BL
AND AL,0FH get the lowest 4 bits
CMP AL,0AH
JB C3
ADD AL,07H
C3: ADD AL,30H
MOV DL,AL show character
MOV AH,02H
INT 21H
MOV DX,OFFSET MES2 show mes2
MOV AH,09H
INT 21H
DW 256 DUP (?) STACK1 ENDSDDATA SEGMENTMES1 DB The least number is: $ MES2 DB 0AH, 0DH, The largest number is: $ NUMB DB 0D9H, 07H, 8BH, 0C5H, 0EBH, 04H, 9DH, 0F9HDDATA ENDSCODE SEGMENT ASSUME CS: CODE, DS: DDATASTART: MOV AX, DDATA MOV DS, AX MOV SI, OFFSET NUMB MOV CX, 0008H JCXZ A4 MOV BH, [SI] MOV BL, BHA1: LODSB AL = DS: [SI], SI = SI+ 1 CMP AL, BH JBE A2 MOV BH, AL JMP A3A2: CMP AL, BL JAE A3 MOV BL, ALA3: LOOP A1A4: MOV DX, OFFSET MES1 show mes1 MOV AH, 09H INT 21H MOV AL, BL show the least number AND AL , 0F0H get the highest 4 bits SHR AL, 4 CMP AL, 0AH JB C2 ADD AL, 07H C2: ADD AL, 30H MOV DL, AL show character MOV AH, 02H INT 21H MOV AL, BL AND AL, 0FH get the lowest 4 bits CMP AL, 0AH JB C3 ADD AL, 07HC3: ADD AL, 30H MOV DL, AL show character MOV AH, 02H INT 21H MOV DX, OFFSET MES2 show mes2 MOV AH, 09H INT 21H (2008-12-25, VHDL, 1KB, 下载5次)
本工程实现的是9位义位与串并变换模块
具体工作过程是：
在时钟CLK的上升沿触发下，从inp端输入接收m序列，按顺序inp->A9->A8->...->A0进行意味，同时把A9，A8，...A0的输出分别给B9，B8，B7,...从而完成串并转换的功能。Q端的信号取自A0的输出短，作为一位4位后的串行m序列信号。
clk为输入时钟信号；inp为接收序列信号输入；Q为串行序列输出；B0~B3为四位并行序列输出。
Realize this project is 9 Sememe transform module with the string and the specific work process is: In the rising edge of CLK clock trigger from inp input receiver m sequence, according to the order of inp- (2008-03-24, VHDL, 242KB, 下载18次)