该代码来自VHDL项目，将NEXYS A7编程为比较器。
This code is from VHDL project the programs a NEXYS A7 to operate as a comparator. (2024-03-21, Others, 0KB, 下载0次)
使用Nexy-A7 100T开发板的UTCN计算机架构实验室的起始代码+文档
Starter code + documentation for the UTCN Computer Architectures laboratories with the Nexy-A7 100T development board (2024-03-06, Others, 0KB, 下载0次)
Nexys A7 FPGA上可编程卵形定时器的Verilog代码
Verilog code for a programmable egg timer on an Nexys A7 FPGA (2024-01-20, Others, 0KB, 下载0次)
C++和Verilog中的8位ALU模拟器，在NEXYS A7 FPGA上实现
8-Bit ALU Simulator in C++ and Verilog, implemented on a NEXYS A7 FPGA (2024-01-18, Others, 0KB, 下载0次)
一个带有M.2 M-Key接口的usb3.0 artix-7 FPGA卡，支持pcileech和riffa等。。。
A pice to usb3.0 artix-7 FPGA card with M.2 M-Key interface, support pcileech and riffa and etc... (2024-01-14, Others, 0KB, 下载0次)
针对Arty A7-100T FPGA板的光滑并行SHA-1哈希饼干。
A sleek parallel SHA-1 hash cracker aimed at the Arty A7-100T FPGA board. (2023-11-10, Others, 0KB, 下载0次)
本项目参考[http:zongyue.top:8090存档aes%E5%92%8Csm4s%E7%9B%92%E5%A4%8D%E5%90%88%E5%9F%E5%AE%9E7%8E%B0%E6%96...]9E%E7%8E%B0%E6%96%B9%E6%B3%95），
This project is referred to http://zongyue.top:8090/archives/aes%E5%92%8Csm4s%E7%9B%92%E5%A4%8D%E5%90%88%E5%9F%9F%E5%AE%9E%E7%8E%B0%E6%96%B9%E6%B3%95 AES verilog exercises made for the basics of S-box generation (2023-10-21, Others, 0KB, 下载0次)
该项目使用Verilog语言在Nexys A7板上实现24小时数字时钟。时间显示在六七段...，
This project implements a 24-hour digital clock on the Nexys A7 board using the Verilog language. The time is displayed on six seven-segment displays. The first two displays show the hours in 24-hour format, the second two displays show the minutes, and the third two displays show the seconds. (2023-09-03, Others, 0KB, 下载0次)
用于FPGA板的Verilog程序，提供各种功能，如工作的7段显示器和纹波进位加法器。，
Verilog Program for our FPGA board that gives various functionalities such as a working 7 segment display and ripple-carry adder., (2023-08-19, Others, 0KB, 下载0次)
基于FPGA的B超数据采集功能，根据输入图像的束同步与帧同步信号，采用中断控制进入FIFO的图像数据的读写操作！
FPGA-based B-data collection capabilities, according to the input image beam synchronization and frame synchronization signal used to control access to FIFO interrupt the operation of image data read and write! (2009-01-10, Others, 3KB, 下载15次)