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[VHDL/FPGA/Verilog] Intro

Mekka ’97 4K Intro The first prize in the work
Mekka ’97 4K Intro The first prize in the work (2014-05-21, Visual C++, 7KB, 下载2次)

http://www.pudn.com/Download/item/id/2548211.html

[VHDL/FPGA/Verilog] a1

实现任意输入公式的真值表计算,同时它也是一个二进制加法器的模拟器，每当在这个模拟器中产生一个二进制数时，就相当于给各个命题变元产生了一组真值指派。
Implement any truth table, enter the formula to calculate, but it is also a binary adder simulator whenever generates a binary number in the simulator, which is equivalent to each propositional variables to produce a set of true value assigned. (2013-12-07, Visual C++, 1KB, 下载4次)

http://www.pudn.com/Download/item/id/2420561.html

[VHDL/FPGA/Verilog] 97

基于FPGA设计ADC0809采样控制器原代码
FPGA-based design ADC0809 sampling controller original code (2012-12-25, Visual C++, 49KB, 下载1次)

http://www.pudn.com/Download/item/id/2095875.html

总计:3