在Arty A7 FPGA上开发的音效项目。
Sound Effects Project developed on Arty A7 FPGA. (2024-02-27, VHDL, 0KB, 下载0次)
布尔诺理工大学VHDL课程
VHDL course at Brno University of Technology (2024-01-06, VHDL, 0KB, 下载0次)
Arty A7 100T FPGA开发板上的SoomRV
SoomRV on the Arty A7 100T FPGA dev board (2023-11-22, VHDL, 0KB, 下载0次)
这是我使用Digilent.的ARTY A7 35T开发板实现的采样器。，
This is my implementation of a Sampler using the ARTY A7 35T developement board by Digilent., (2022-04-15, VHDL, 0KB, 下载0次)
创建一个使用brainf*ck语言作为操作码的处理器的vhdl实验，
A vhdl experiment of creating a processor that uses the brainf*ck language as its opcodes, (2023-07-30, VHDL, 0KB, 下载0次)
用于Xilinx FPGA的Hastlayer硬件侧组件。有关详细信息，请参阅<https://hastlayer.com>。
用于Xilinx FPGA的Hastlayer硬件侧组件。有关详细信息，请参阅<https://hastlayer.com>。 (2022-10-09, VHDL, 751KB, 下载0次)
GRLIB GPL支持Digilent CMOD A7 35T板
GRLIB GPL support for Digilent CMOD A7 35T board (2020-01-05, VHDL, 2651KB, 下载0次)
用于VHDL的GNSS代码和信号生成。GPS（L1 C A、L5）、伽利略（E1OS、E5）。包括Xilinx ISE测试台和wa...
GNSS codes and signal generation for VHDL. GPS (L1 C/A, L5), Galileo (E1OS, E5). Includes Xilinx ISE testbench and wave configuration files. (2018-01-03, VHDL, 88KB, 下载0次)
VHDL代码，用于生成GPS L1 C A和Galileo E1OS和E5 PRN以及无数据信号。不包括辅助代码。
VHDL codes to generate GPS L1 C A and Galileo E1OS and E5 PRNs and dataless signals. Secondary codes not included. (2019-02-22, VHDL, 782KB, 下载0次)
MRISC32 ISA的流水线有序标量VHDL实现
A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA (2023-03-30, VHDL, 293KB, 下载0次)
一种基于MRISC32-A1 CPU的计算机（FPGA SoC）
A computer (FPGA SoC) based on the MRISC32-A1 CPU (2023-03-30, VHDL, 385KB, 下载0次)
布尔诺理工大学VHDL课程
VHDL course at Brno University of Technology (2023-05-07, VHDL, 10263KB, 下载0次)
用于测试IIC传感器的温度和相对湿度读数的不同实现方式的小型FPGA项目
A small FPGA project of different implementations for testing Temperature and Relative Humidity readings of a IIC sensor (2023-04-30, VHDL, 70588KB, 下载0次)
（您自己的数字加速器）通过使用有限脉冲响应（FIR）和低通滤波器（LPF...
(Your Own Digital Accelerator) A Smoothing filter by using a Finite Impulse Response (FIR) and a Low Pass Filter (LPF) algorithm. The hardware used is a NEXYS A7 Field Programmable Gate Array (FPGA) programmedin Verilog. (2020-07-25, VHDL, 13044KB, 下载0次)
ZX Spectrum的端口Digilent Nexys A7-100T板的下一个核心。
Port of the ZX Spectrum Next core to the Digilent Nexys A7-100T board. (2022-03-16, VHDL, 113226KB, 下载0次)
这是电子设计大赛的97年b题简易数字频率计的fpga一种做法。
This is Electronic Design Competition 1997 b problem simple digital frequency meter fpga practice. (2011-08-11, VHDL, 471KB, 下载76次)
Xilinx芯片所有关于PCI Express接口的DMA源代码，包含相关的配套的文档资料。
Xilinx chip on the PCI Express interface for all DMA source code, including relevant supporting documentation. (2010-11-24, VHDL, 30112KB, 下载718次)
SDH开销的接收处理，要求：
1， A1和A2字节为帧头指示字节，A1为“11110110”，A2为“00101000”，连续3个A1字节后跟连续3个A2字节表示SDH一帧的开始。要求自行设计状态机，从连续传输的SDH字节流中找出帧头。
2， E2字节为勤务话通道开销，用于公务联络语音通道，其比特串行速率为64KHz(8*8K=64)。要求从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟，其中64K时钟要求基本均匀。（输出端口包括串行数据和64K串行时钟）
Receiving SDH overhead processing requirements: 1, A1 and A2 bytes instruction byte header, A1 is " 11110110" , A2 is " 00101000" , for three consecutive A1 bytes followed by three A2 bytes of an SDH the beginning of the frame. Asked to design a state machine, from the continuous stream of bytes in the SDH transmission header to find out. 2, E2-byte path overhead for the service, then, for the public to contact voice channels, the bit-serial rate 64KHz (8* 8K = 64). SDH byte stream request from the extraction E2 bytes, and the serial output in accordance with rates of E2 64K stream and clock, which clock requires 64K basic uniform. (Including the serial data output port and 64K serial clock) (2010-11-05, VHDL, 2KB, 下载107次)
基于FPGA的多相滤波器设计
摘要: 以脉冲多普勒雷达信号处理为背景,研究了数字多相滤波器的特点和设计方法 进而研究数字多相滤波器的数字仿真
方法与 FPGA 实现技术 对于自主研究 设计和实现雷达信号处理的各种结构的滤波器具有重要的意义
Based FPGA multiphase Filter Design Abstract: Pulse Doppler signal processing background studied digital polyphase filter characteristics and design method then research digital multiphase filter Digital Simulation Method and FPGA Realization Technology For autonomous research design and realization radar signal processing various structures filter great significance (2010-04-01, VHDL, 315KB, 下载140次)
這是一個DWT的Verilog code,它的主要功用是PC與FPGA之間的DWT程序的溝通與傳輸
This is a DWT of the Verilog code, its main function is between the PC and FPGA communication DWT procedures and transmission (2008-03-28, VHDL, 1433KB, 下载282次)