在Nexys 4 DDR Nexys A7 FPGA训练器上使用DDR2内存和MIG IP的示例
Example using DDR2 memory and MIG IP on the Nexys 4 DDR Nexys A7 FPGA Trainer (2022-06-07, Verilog, 5090KB, 下载0次)
njtech数字设计。基于Nexys A7 100T的fpga数字报警系统
njtech digital design. a fpga digital alarm system with Nexys A7 100T (2019-06-11, Verilog, 2613KB, 下载0次)
这个项目的目的是模仿一个篮球记分板，有计时器和两个团队的得分。请参阅pi的自述文件...
Objective of this project was to emulate a Basketball score board, with timer and two teams scores. See readme for pic and more details. Release published v1.0.5 (2023-05-29, Verilog, 2216KB, 下载0次)
利用FPGA通过SPI接口配置SONY IMX264图像传感器，按照全画幅输出图像。XILINX A7平台实测
Using FPGA to config SONY IMX264 CMOS image sensor through SPI interface (2019-12-05, Verilog, 3KB, 下载14次)
本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出
In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output (2019-05-06, Verilog, 15402KB, 下载3次)
128×160规格TFT显示屏显示图片的源代码
128 x 160 specifications TFT display picture of the source code (2018-08-18, Verilog, 6586KB, 下载3次)
基于verilog编写的MSK调制程序，modsim仿真波形正确
Verilog based MSK modulation program written, modsim simulation waveform correct (2018-04-26, Verilog, 1059KB, 下载26次)
xilinx FPGA A7 驱动DDR3的DEMO例程
DEMO routines driven by Xilinx FPGA A7 for DDR3 (2018-04-13, Verilog, 23789KB, 下载14次)
VERILOG编程指导书，针对于vivado编程应用
VERILOG programming guide for the application of vivado programming (2017-12-17, Verilog, 3182KB, 下载8次)
用于测试FPGA串口接收，带singelTap。便于观测。
Used to test the FPGA serial port reception, with singelTap. Convenient observation. (2017-07-28, Verilog, 6463KB, 下载1次)