28M分频器
D触发器
jk触发器
library ieee
library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_arith.all
use ieee.std_logic_unsigned.all
entity ymq is
port(num:in std_logic_vector(3 downto 0)
dout:out std_logic_vector(0 TO 6))
end ymq
architecture a1 of ymq is
begin (2012-04-11, Visual C++, 1KB, 下载3次)