该模块的工作原理是把来自并行输入与状态控制模块的两组并行输出信号进行高低为对应的电平比较。
若对应状态相同则输出为1，否则为0。图中A0-A9为A组并行码；clk0为时钟信号，z为比较输出。
The module is the working principle is to parallel input from state control module with two sets of parallel output signals corresponding to high and low level for comparison. If the corresponding state of the same output as one, otherwise to 0. Map A0-A9 parallel code for the A group clk0 for the clock signal, z In order to compare the output. (2008-03-24, VHDL, 255KB, 下载4次)