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按平台查找All Verilog(11) 

[VHDL/FPGA/Verilog] 数字时钟

实现计时,置数,闹钟设置,切换显示等 1.硬件资源:FPGA开发板一块,电源线一根,下载器一个 2.开发板用到的资源:三颗独立按键,一位拨码开关,八位七段数码显示器, 蜂鸣器 3.功能设计:时钟功能,校时功能,闹钟功能 整个系统分为7大模块
Realize timing, setting, alarm setting, switching display, etc 1. Hardware resources: one FPGA development board, one power cord and one Downloader 2. Resources used in the development board: three independent buttons, one dial switch, eight seven segment digital display, Buzzer 3. Function design: clock function, timing function, alarm function The whole system is divided into seven modules (2020-06-16, Verilog, 2381KB, 下载0次)

http://www.pudn.com/Download/item/id/1592316460299449.html

[处理器开发] zuoye3

选择最大的输入,最后输出最大的数据,这个程序是在校研究生写的
Select the largest input, and finally output the largest data. This program is written by graduate students in school (2020-03-31, Verilog, 94KB, 下载0次)

http://www.pudn.com/Download/item/id/1585615260806461.html

[其他] shuzidianzizhong

数字时钟电路走时,校时,去抖,分频,整点报时
Digital clock circuit travel time, the school, to shake, frequency division, the hour (2019-07-09, Verilog, 1302KB, 下载0次)

http://www.pudn.com/Download/item/id/1562658631397468.html

[VHDL/FPGA/Verilog] shixunlaozhong

程序是实现一个数字钟,有进位、清零、校时与校分功能。数字钟的分钟和小时是用数码管显示
COUNTER AND ALARMProblem C. Cave Escape Google Kickstart Round G 2018 [Small Input] (2019-04-26, Verilog, 1599KB, 下载1次)

http://www.pudn.com/Download/item/id/1556211131941372.html

[VHDL/FPGA/Verilog] clock

实现一个24小时制的数字时钟,可切换校时模式,带有闹钟和整点报时功能,约束文件基于basys2实验板
A 24-hour digital clock with alarm clock and full-time alarm function can be switched. The constraint file is based on the basys2 experimental board. (2018-12-30, Verilog, 36571KB, 下载3次)

http://www.pudn.com/Download/item/id/1546179133630093.html

[其他] watch

可以显示年月日时分秒周的万年历,在此基础上电子表有两种模式,计时和校时模块。
Can every week calendar date when the show, based on the electronic watch has two modes, and the timing module timing. (2018-05-24, Verilog, 3KB, 下载1次)

http://www.pudn.com/Download/item/id/1527131524720976.html

[VHDL/FPGA/Verilog] clock

12制 24制可切换电子钟,有时分秒,都可校时
clock can adjust minute,hour,seconds (2018-05-11, Verilog, 747KB, 下载1次)

http://www.pudn.com/Download/item/id/1526020302304768.html

[VHDL/FPGA/Verilog] digital_clock

自己用verilog HDL写的一个数字钟模块,包括校时功能,在Maxplusii下调试和下载通过
A digital clock module written by Verilog HDL, including timing function, debugging and downloading through Maxplusii. (2018-04-13, Verilog, 3KB, 下载2次)

http://www.pudn.com/Download/item/id/1523579620317334.html

[VHDL/FPGA/Verilog] DIGITALCLOCK

多功能数字种 可实现校时 闹钟 整点报时等功能
Multi-function digital species can realize the function of time alarm clock and other functions (2018-02-10, Verilog, 2KB, 下载2次)

http://www.pudn.com/Download/item/id/1518242973669246.html

[VHDL/FPGA/Verilog] clock

自己开发的电子时钟小程序,通过数码管显示时间,key1和key2控制校时校分,key3切换时钟模式和闹钟模式,切换到闹钟模式再按key1和key2即可设定闹钟时间。key4控制开启/关闭闹钟。有整点报时功能。
Self developed electronic clock applet, through the digital tube display time, key1 and key2 control time correction, Key3 switch clock mode and alarm mode, switch to the alarm mode, then press key1 and key2 can set the alarm time. Key4 controls the opening / closing of the alarm clock. There is a whole time function. (2017-12-06, Verilog, 9120KB, 下载2次)

http://www.pudn.com/Download/item/id/1512561478821722.html

[其他] zx

电子时钟,具有校时校分、设定闹钟、计时的功能
The electronic clock has the function of adjusting time, setting alarm clock and timing (2017-09-11, Verilog, 4505KB, 下载1次)

http://www.pudn.com/Download/item/id/1505128100666182.html
总计:11