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[VHDL/FPGA/Verilog] clock

clk: 标准时钟信号,本例中,其频率为4Hz; clk_1k: 产生闹铃音、报时音的时钟信号,本例中其频率为1024Hz; mode: 功能控制信号;为0:计时功能; 为1:闹钟功能; 为2:手动校时功能; turn: 接按键,在手动校时功能时,选择是调整小时,还是分钟; 若长时间按住该键,还可使秒信号清零,用于精确调时; change: 接按键,手动调整时,每按一次,计数器加1; 如果长按,则连续快速加1,用于快速调时和定时; hour,min,sec :此三信号分别输出并显示时、分、秒信号, 皆采用BCD码计数,分别驱动6个数码管显示时间; alert: 输出到扬声器的信号,用于产生闹铃音和报时音; 闹铃音为持续20秒的急促的"嘀嘀嘀"音,若按住"change"键, 则可屏蔽该音;整点报时音为"嘀嘀嘀嘀-嘟"四短一长音; LD_alert: 接发光二极管,指示是否设置了闹钟功能; LD_hour: 接发光二极管,指示当前调整的是小时信号; LD_min: 接发光二极管,指示当前调整的是分钟信号。
clk: standard clock signal, in this case, the frequency of 4Hz clk_1k: generate the alarm sound, chime sound clock signal, in this case the frequency of 1024Hz mode: Functional control signal 0: Chronograph function 1: The alarm clock function 2: Manually school-time functionality turn: access keys manually school function, the choice is to adjust hours or minutes If you long press the key, also make clear of the second signal for precise tone change: access key, and manually adjust each time you press the counter plus 1 If long, then in quick succession plus one for fast tune and timing hour, min, sec: This signal is output and display hours, minutes and seconds signal, All use a BCD count, drive six digital display time alert: Output signal to the speaker used to generate the alarm tone chime sound The alarm tone for the last 20 seconds of rapid beeping beep "tone, if hold down the" change "button, Can be shielded from the sound the whole point timekeeping w (2012-03-05, Windows_Unix, 480KB, 下载4次)

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