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[VHDL/FPGA/Verilog] D_Clock

数字钟的主要功能有年月日时分秒的显示输出功能和对日期及时间进行设置的功能,还可以有整点报时等功能。设计数字钟的核心问题是时钟日期的自动转换功能。即自动识别不同月份的天数的控制。据此可以设计一个如图1所示结构的数字钟,该数字钟包括校时模块、时分秒计时模块、年月日模块、和输出选择模块。
digital clock is the main function Minutes date when the output function and the date and time set for the function , they can point the entire timekeeping functions. Digital Clock Design is the core issue date of the clock automatic conversion function. Automatic identification is the number of days in the control. One can design a structure as shown in figure 1 of the digital clock, the digital clock module, including school, a time when every minute module, Date module, and choose the output module. (2007-04-16, Delphi, 372KB, 下载59次)

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