数字电路时间以12小时为一个周期，显示时、分、秒，具有校时功能，可以分别对时及分进行单独校时，使其校正到标准
时间计时过程具有报时功能，当时间到达整点前10秒进行蜂鸣报时
SHUZISHIZHONG (2012-12-10, MultiPlatform, 3873KB, 下载10次)
这是我电子线路测试的作业，在FPGA板上实现数字钟，（Max2环境）采用VHDL语言编写，非常适合初学者。具备24小时计时，校时，低高音整点报时，定时和多重功能选择的功能。
This is my test of electronic circuits operating at the FPGA board digital clock (Max2 Environment) using VHDL language, very suitable for beginners. 24-hour time, the school, the whole point of low Treble timekeeping, the timing and choice of multiple functional function. (2007-01-31, MultiPlatform, 495KB, 下载26次)
用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能
Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock (2005-12-10, MultiPlatform, 2KB, 下载709次)