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[机器人/智能制造] AX7Z010B_2023

AX7Z010B板广泛应用于安防监控、汽车电子、机器视觉、智能制造、视音频采集与处理、医疗设备、仪器仪表、智能电网、数据中心等行业。
AX7Z010B board is widely used in security monitoring, automotive electronics, machine vision, intelligent manufacturing, video and audio acquisition and processing, medical equipment, instrumentation, smart grid, data center and other industries. (2024-02-24, VHDL, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1708745145553345.html

[机器人/智能制造] AX7Z020B_2023

AX7Z020B板广泛应用于安防监控、汽车电子、机器视觉、智能制造、视音频采集与处理、医疗设备、仪器仪表、智能电网、数据中心等行业。
AX7Z020B board is widely used in security monitoring, automotive electronics, machine vision, intelligent manufacturing, video and audio acquisition and processing, medical equipment, instrumentation, smart grid, data center and other industries. (2024-02-24, VHDL, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1708745142583774.html

[机器人/智能制造] AX7Z010_2023

AX7Z010板广泛应用于安防监控、汽车电子、机器视觉、智能制造、视音频采集与处理、医疗设备、仪器仪表、智能电网、数据中心等行业。
AX7Z010 board is widely used in security monitoring, automotive electronics, machine vision, intelligent manufacturing, video and audio acquisition and processing, medical equipment, instrumentation, smart grid, data center and other industries. (2024-02-08, VHDL, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1707365431621695.html

[机器人/智能制造] AX7Z020_2023

AX7Z020板广泛应用于安防监控、汽车电子、机器视觉、智能制造、视音频采集与处理、医疗设备、仪器仪表、智能电网、数据中心等行业。
AX7Z020 board is widely used in security monitoring, automotive electronics, machine vision, intelligent manufacturing, video and audio acquisition and processing, medical equipment, instrumentation, smart grid, data center and other industries. (2024-02-08, VHDL, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1707365428423374.html

[VHDL/FPGA/Verilog] l0mdt-hdl-design

为我们的学生和其他人克隆欧洲核子研究中心报告,
Clone of CERN repo for our students and other people, (2023-08-09, VHDL, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1694141676702089.html

[collect] radar_data_Kmeans

雷达信号分选任务是对雷达脉冲序列进行K-means聚类,以判定每个脉冲的所属雷达 1、对 2GHz 以内的信号进行多项滤波,以确定信号的中心频带 2、构建分选数据集,对场景中雷达脉冲序列信号进行仿真,并通过UDP传至开发处理 3、基于C++实现K-means算法并部署到ZY...,
The radar signal sorting task is to K-means cluster the radar pulse sequence to determine the radar to which each pulse belongs. 1. Multi filter the signal within 2GHz to determine the central band of the signal. 2. Build sorting data sets, simulate the radar pulse sequence signal in the scene, and send it to the development process through UDP. 3. Implement the K-means algorithm based on C++and deploy it to ZY, (2023-08-17, VHDL, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1692285188144254.html

[VHDL/FPGA/Verilog] nesfpga

任天堂娱乐系统的一种简单FPGA实现
A Simple FPGA Implementation of the Nintendo Entertainment System (2018-10-28, VHDL, 1217KB, 下载0次)

http://www.pudn.com/Download/item/id/1540662967304622.html

[文章/文档] ZeBu Server 4

ZeBu Server 4:行业速度领先的硬件仿真系统 ZeBu? Server 4 仿真系统建立在经过验证的 ZeBu 快速仿真架构之上,仿真性能超出同类竞争仿真解决方案 2 倍,可实现 SoC 验证和软件启动,并满足汽车、5G、网络、人工智能和数据中心 SoC 的海量验证要求。ZeBu Server 4 的功耗降低了 5 倍,数据中心占用空间减少了一半,具有业内非常低的持有成本。 此外,Z (2022-05-20, VHDL, 332KB, 下载0次)

http://www.pudn.com/Download/item/id/1653027540367369.html

[VHDL/FPGA/Verilog] dave3d_development_kit_altera_1.2.4.4_20130902

tes dst 的D/AVE 3d加速核心 D/AVE 3D是3D图形应用的经济高效的IP核心。该核心可用于FPGA、ASIC和SOC,专门为嵌入式、汽车和信息娱乐市场设计,重点强调硬件和软件的灵活性。
D/AVE 3D is cost-efficient IP core for 3D graphics applications. This core is available for FPGAs, ASICs and SOCs, specifically designed for the embedded, automotive and infotainment market with a big emphasis on flexibility both in hardware and the software. (2019-04-08, VHDL, 36829KB, 下载0次)

http://www.pudn.com/Download/item/id/1554671162981907.html

[其他] csacsacsac

聚星娱乐总代【768-078】距离中国最遥远的国家 你知道是哪里吗?,帜挪韶纳此,刘亦菲妈妈素颜证件照曝光 皮肤白皙美貌惊人,吓呈章锥蜗,塔利斯卡恒大薪水或达1000万欧 远超曼联报价,捕酪咨乇蕴
vdzvxczxgxvzfbvxcbxcvbxvcvxcbgffbxbxcv (2018-06-30, VHDL, 1KB, 下载0次)

http://www.pudn.com/Download/item/id/1530348712408714.html

[其他] CIC VHDL language

台湾国家芯片系统中心专用教程,陈献文著作
taiwan CIC advanced VHDL course (2017-10-11, VHDL, 2849KB, 下载1次)

http://www.pudn.com/Download/item/id/1507723872208348.html

[VHDL/FPGA/Verilog] CIC_filter

抽取:(接收端) 中频信号IF 20M(采样率是50M) 下变频信号 MIX_O 1M(50M) 采用CIC滤波器进行降采样率。 插值:(发送端) 基带信号上变频到1M,采样率是2.5M,采用CIC滤波器进行升采样率处理。 注释:升采样率或者降采样率不会改变原始信号的中心频率,但是频谱分布会发生改变。
Extraction: (receiver) IF signal 20M (sampling rate is 50M) down-conversion signal MIX_O 1M (50M) using CIC filter down sampling rate. Interpolation: (sending side) Baseband signal up to 1M, the sampling rate is 2.5M, using CIC filter for sampling rate processing. Note: The up-sampling rate or down-sampling rate does not change the center frequency of the original signal, but the spectral distribution will change. (2016-12-01, VHDL, 9472KB, 下载12次)

http://www.pudn.com/Download/item/id/1480574210857743.html

[VHDL/FPGA/Verilog] 10.2LCD_display-04

应用于车载系统娱乐设施,控制图像RGB数据在LCD屏上点屏,包括LCD的点屏时序控制,以及相关的LCD屏配置信息
Used in vehicle system entertainment facilities, control the RGB image data on the LCD screen, including point of LCD screen sequential control, and related LCD configuration information (2016-08-22, VHDL, 12529KB, 下载2次)

http://www.pudn.com/Download/item/id/1471848925527968.html

[VHDL/FPGA/Verilog] Verilog

最经典的VHDL学习资料,千万不要错过哦。夏永闻主编的那本书,不想买书的速来
VHDL learning the most exciting tutorials do not miss it (2016-06-25, VHDL, 22257KB, 下载1次)

http://www.pudn.com/Download/item/id/1466855188304765.html

[单片机开发] contest

用单片机和FPGA控制的一个游戏控制系统 数码管:不足百位的黑掉 得分后自动切换显示 开关功能: 0:开始游戏:球归中心点,并自动发球。发球方向将与开关1状态有关 1:控制发球方向:游戏中也可以控制 2: 休闲模式:开启后小球将左右自动反弹,不需要按住键 3:球向左下角移动 4:球向右上角移动 5: 6: 7:切换数码管显示的队及得分 按钮: 0:右侧挡板按下(玩家1) 1: 2: 3:左侧挡板按下(玩家2)
A game control system controlled by FPGA and microcontroller (2015-07-08, VHDL, 9639KB, 下载5次)

http://www.pudn.com/Download/item/id/1436347294220134.html

[VHDL/FPGA/Verilog] video_center_scan_scaler_alpha_blend

本工程实现两路视频信号阿尔法通道混合(alpha blend), 视频信号黑点中心 点扫描定位,期间用到视频帧缓存(frame cache)、视频信号缩放(scaler)等,且用到ram、DDR2等作为缓存,是很值得参考的视频图像处理工程。
scaler,alpha blend,ddr2 controller,center scan, frame cache, dpram, etc by verilog, include code and discription (2015-06-20, VHDL, 8283KB, 下载30次)

http://www.pudn.com/Download/item/id/1434777650209166.html

[游戏] bahe2

拔河游戏机, 1、 设计一个能进行拔河游戏的电路。 2、 电路使用15个(或9个)发光二极管,开机后只有中间一个发亮,此即拔河的中心点。 3、 游戏双方各持一个按钮,迅速地、不断地按动,产生脉冲,谁按得快,亮点就向谁的方向移动,每按一次,亮点移动一次。 4、 亮点移到任一方终端二极管时,这一方就获胜,此时双方按钮均无作用,输出保持,只有复位后才使亮点恢复到中心。 5、 用数码管显示获胜者的盘数。 教学提示: 1、 按钮信号即输入的脉冲信号,每按一次按钮都应能进行有效的计数。 2、 用可逆计数器的加、减计数输入端分别接受两路脉冲信号,可逆计数器原始输出状态为0000,经译码器输出,使中间一只二极管发亮。 3、 当计数器进行加法计数时,亮点向右移;进行减法计数时,亮点向左移。 4、 由一个控制电路指示谁胜谁负,当亮点移到任一方终端时,由控制电路产生一个信号,使计数器停止计数。 5、 将双方终端二极管“点亮”信号分别接两个计数器的“使能”端,当一方取胜时,相应的计数器进行一次计数,这样得到双方取胜次数的显示。 6、 设置一个“复位”按钮,使亮点回到中心,取胜计数器也要设置一个“复位”按钮,使之能清零。
1, the design of a circuit can be a tug of war game. 2, the circuit using the 15 (or 9) light-emitting diodes, after only among a shiny, namely the center of a tug of war. 3, the game with a two button rapidly and continuously pressed, generates a pulse, who by fast, highlight moves to whom the direction each time, the highlight moves once. 4, the highlight moves to either terminal diode, this party would win, this time the two sides button had no effect, the output remains only reset after making the highlight back to the center. 5, with digital display plate number winner. Teaching tips: 1, the signal that is input pulse signal button, each press of the button should be able to effectively counter. 2, with a reversible counter, plus or minus count input pulse signal, respectively, to receive two-way, reversible counter status for the 0000 original output by the decoder output, so that the middle one diode lights up. 3, when the counter counts up, the highlight to the right When subt (2014-06-18, VHDL, 443KB, 下载14次)

http://www.pudn.com/Download/item/id/2569822.html

[VHDL/FPGA/Verilog] zhongji

基本要求: 1、设计一个能进行拔河游戏的电路。 2、电路使用9个发光二极管,开机后只有中间一个发亮,此即拔河的中心点。 3、游戏双方各持一个按钮,迅速地、不断地按动,产生脉冲,谁按得快,亮点就向谁的方向移动,每按一次,亮点移动一次。 4、亮点移到任一方终端二极管时,这一方就获胜,此时双方按钮均无作用,输出保持,只有复位后才使亮点恢复到中心。 5、用数码管显示获胜者的盘数。
Basic requirements: 1, the design of a circuit capable of tug of war game. 2, the circuit uses nine light-emitting diodes, only the middle of a shiny-war. 3, the game with a two button rapidly and continuously pressed, generates a pulse, who by fast, highlight a direction on who to move, each time, the highlight moves again. 4, the highlight moves to either terminal diode, this side will win, this time the two sides had no effect button, output remains only reset after the highlight back to center. 5, with digital display winner of the plate number. (2013-10-16, VHDL, 1989KB, 下载6次)

http://www.pudn.com/Download/item/id/2375647.html

[VHDL/FPGA/Verilog] generate-coordinates

使用VHDL编写语言,巧妙的利用计数器和循环输出一个坐标系,由于VHDL出现负数比较麻烦,全部由正数代替,输出一个原点在中心,半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。
Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive number, the output an origin at the center, radius 128 256 256 coordinates. Convenient coordinate transformation and coordinate to do with this algorithm. (2013-08-28, VHDL, 1KB, 下载3次)

http://www.pudn.com/Download/item/id/2341225.html

[VHDL/FPGA/Verilog] TrafficLight

通过硬件描述语言VHDL编程,实现交通灯功能,要求如下:   ① 车辆传感器(C),检测车辆通行情况,用于主干道的优先权控制; ② 主干道公路路口安装有人员通过请求按钮(PQ),一旦有请求信息,控制器应按放行处理,否则按默认方式处理; ③ Online控制信号由交通控制中心发出,(Online=1)一旦它有效,则主干道放行,十字交叉路口控制器“失效”,Online=0十字交叉路口控制器恢复控制权;   ④ 当次干道公路无车时,始终保持次干道公路红灯亮,主干道绿灯亮; ⑤ 当次干道公路有车时,而主干道通车时间已经超过它的最短通车时间时,禁止主干道通行,让次干道公路通行。主干道最短通车时间为25s ; ⑥ 当次干道公路和主干道都有车时,按主干道通车25s,次干道公路通车16s交替进行;   ⑦ 不论主干道情况如何,次干道公路通车最长时间为16s; ⑧ 在每次由绿灯亮变成红灯亮的转换过程中,要亮5s时间的黄灯作为过渡; ⑨ 用两组开关代替传感器作为检测人员通过请求和车辆是否到来的信号。用红、绿、黄三种颜色的发光二极管作交通灯;   ⑩ 要求显示时间,倒计时。
Through hardware description language VHDL programming, traffic lights functional requirements are as follows: ① vehicle sensors (C), detection of vehicle traffic situation, the priority control for the main road ② trunk road junctions equipped with staff through a request button (PQ), if there is a request message, the controller should be released, otherwise handled by default ③ Online control signal issued by the traffic control center, (Online = 1) if it is valid, trunk release, cross the intersection Controller "failure", Online = 0 crossroad controller resumes control over ④ When the secondary trunk road no car, and always maintain secondary roads road red light, green light main road ⑤ When the secondary trunk road with the car, while the trunk opening time has exceeded its minimum opening time, prohibited roads impassable, so that secondary roads roads impassable. Trunk shortest time for the opening 25s ⑥ When the sub-trunk roads and main roads have vehicle, accordin (2013-07-13, VHDL, 8713KB, 下载7次)

http://www.pudn.com/Download/item/id/2304276.html
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