一个有趣的32位PowerPC类Linux RISC CPU，用于FPGA娱乐目的，
A for-fun 32-bit PowerPC -like Linux-capable RISC CPU for FPGA entertainment purposes, (2022-08-21, Verilog, 0KB, 下载0次)
任天堂娱乐系统（NES）Famicom Famiclones芯片反转
Nintendo Entertainment System (NES) Famicom Famiclones chip reversing (2023-06-07, Verilog, 0KB, 下载0次)
一种用于高性能超图处理的数据中心加速器
A Data-Centric Accelerator for High-Performance Hypergraph Processing (2022-08-20, Verilog, 19643KB, 下载0次)
电机驱动的Verilog代码。将包括中心对齐PWM、增量编码器等verilog代码
Verilog code for motor drives. Will include center-aligned PWM, incremental encoder, etc verilog codes (2021-09-09, Verilog, 17KB, 下载0次)
双发RV64IM处理器，娱乐和学习
Dual-issue RV64IM processor for fun & learning (2023-01-18, Verilog, 6360KB, 下载0次)
任天堂娱乐系统（NES）兼容FPGA核心
Nintendo Entertainment System (NES) compatible FPGA core (2020-06-02, Verilog, 346KB, 下载0次)
[日期2022]PowerGear:通过异构边缘中心GNN在FPGA HLS中进行早期功率估计
[DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs (2022-04-15, Verilog, 299664KB, 下载0次)
NESTang是一款用Sipeed Tang Nano 20K和Primer 20K板实现的FPGA任天堂娱乐系统
NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Nano 20K and Primer 20K boards (2023-05-19, Verilog, 758KB, 下载0次)
基于FPGA的任天堂娱乐系统仿真器
FPGA-based Nintendo Entertainment System Emulator (2022-06-28, Verilog, 1346KB, 下载0次)
用于以空间为中心的CNN DPU研究和开发的开源示例FPGA VHDL代码
Open Source Example FPGA VHDL code for Space Centric CNN DPU Research and Development (2022-03-28, Verilog, 1576KB, 下载0次)
Project Costanza是一款以Verilog中的DE0 Nano FPGA为中心从头开始构建的视频游戏机
Project Costanza is a video game console built from the ground up centered around the DE0-Nano FPGA in Verilog (2014-08-12, Verilog, 1543KB, 下载0次)
DISE O de SISTEMAS DIGITALES EN VERILOG USANDO FPGAS库的材料。中心：CTIF马德里首都，2018
Material del curso de DISE O DE SISTEMAS DIGITALES EN VERILOG USANDO FPGAS LIBRES. Centro: CTIF Madrid-capital, 2018 (2018-05-31, Verilog, 9632KB, 下载0次)
乐鑫科技提前批题目，这里采用状态机的写法
Lexin technology approved the topic in advance, here using the state machine writing method (2020-07-09, Verilog, 2KB, 下载0次)
包括数码管、按键、开关、LED等、UART串口等程序。
Including digital tube, key, switch, LED, UART serial port and other programs. (2018-12-12, Verilog, 1169KB, 下载1次)
状态机由状态寄存器和组合逻辑电路构成，能够根据控制信号按照预先设定的状态进行状态转移，是协调相关信号动作、完成特定操作的控制中心.
The state machine is composed of state register and combinational logic circuit. It can transfer state according to the state of control according to the predefined state. It is the control center that coordinates the action of related signal and completes the specific operation. (2018-05-04, Verilog, 5805KB, 下载0次)
电路使用15个发光二极管表示拔河的“电子绳”，开机后只有中间一个二级管亮，此点为拔河的中心点。
（2）游戏双方各持一个按钮，迅速地、不断地按动，产生脉冲，谁按得快，亮点就向谁的方向移动，每按一次，亮点移动一次。
（3）亮点移到任一方终端二极管时，这一方就获胜，此时双方按钮均无作用，输出保持，只有复位后才使亮点恢复到中心。
（4）由裁判下达比赛开始命令后（即总的使能端控制），甲乙双方才能输入信号，否则，输入信号无效。
（5）用数码管显示获胜者的盘数，每次比赛结束自动给获胜方加分。
（6）比赛结束时，播放音乐，存储两首以上的音乐，滚动播放，或者根据不同获胜方播放不同音乐
The circuit uses 15 light-emitting diodes to represent the "electronic rope" of tug of war. After launching, there is only one two stage tube in the middle, which is the central point of tug of war.
(2) the two sides of the game each hold a button, quickly and constantly press, produce pulse, who press fast, the bright spot moves to whose direction, every time, the bright spot moves once.
(3) when the bright spot is moved to the terminal diode of the one side, the party wins, when both buttons do not work, the output is kept and the bright spot is restored to the center only after the reset.
(4) after the order is issued by the referee, the input and output signals can be input by both sides, otherwise, the input signal is invalid.
(5) the number of digital tube display, automatically to the winner of each game end points.
(6) at the end of the game, play music, store more than two music, scroll play, or play different music according to different winners. (2018-04-10, Verilog, 976KB, 下载1次)
本文是台湾国家晶元设计中心的内部培训资料，对于基础学习和进阶学习都有很大帮助
This is the Taiwan national Jingyuan design center internal training materials, are of great help for basic learning and advanced learning (2017-10-07, Verilog, 2945KB, 下载3次)