ECSE-6680项目：伦斯勒理工学院张彤教授的高级VLSI设计
Projects for ECSE-6680: Advanced VLSI Design with Professor Tong Zhang at Rensselaer Polytechnic Institute (2024-03-15, SystemVerilog, 0KB, 下载0次)
我在威斯康星大学麦迪逊分校（UW-Madison）修的ECE课程。介绍HDL和自动合成在设计中的使用。先进的设计原则。Verilog和VHDL描述语言。从硬件描述语言合成。面向时间的合成。集成电路布局与面向时序设计的关系。为重用而设计。
A ECE course where I ve taken in UW-Madison. Introduction to the use of HDL and automated synthesis in design. Advanced design principles. Verilog and VHDL description languages. Synthesis from hardware description languages. Timing-oriented synthesis. Relation of integrated circuit layout to timing-oriented design. Design for reuse. (2024-03-13, SystemVerilog, 0KB, 下载0次)
我的RV32I处理器的实现基于教材-数字设计和计算机架构：RISC-V版的莎拉哈里斯…
My implementation of the RV32I processor based on the Textbook - Digital Design and Computer Architecture: RISC-V Edition by Sarah Harris… (2024-01-19, SystemVerilog, 0KB, 下载0次)
fpga俄罗斯方块
fpga tetris (2023-12-19, SystemVerilog, 0KB, 下载0次)
基于UVM的全加器（1位加法器）电路验证测试台。，
UVM based testbench for verification of Full adder (1-bit adder) circuit ., (2023-09-29, SystemVerilog, 0KB, 下载0次)
维罗格，
VERILOG, (2023-09-07, SystemVerilog, 0KB, 下载0次)
米普斯科尔，，
mipscore,, (2023-07-30, SystemVerilog, 0KB, 下载0次)
新加坡，，
sne,, (2022-11-23, SystemVerilog, 0KB, 下载0次)
Bresenham的直线算法是一种线绘制算法，它确定应在o...中选择的n维光栅的点...，
Bresenham s line algorithm is a line drawing algorithm that determines the points of an n-dimensional raster that should be selected in order to form a close approximation to a straight line between two points. It is commonly used to draw line primitives. (2022-10-18, SystemVerilog, 0KB, 下载0次)
CIC-560步进电机FPGA驱动程序用于普兰司琼样品一维定位训练系统的设计
FPGA driver of step motor on CIC-560 training system designing for plazmatrone sample 1-d positioning (2019-02-01, SystemVerilog, 16KB, 下载0次)
RSA加解密的硬件实现，在FPGA上测试
Hardware implementation of RSA Encryption Decryption, tested on FPGA (2019-09-23, SystemVerilog, 8KB, 下载0次)
SystemVerilog设计使用DE10 Lite FPGA开发板上的加速度计
SystemVerilog design to use the accelerometer on the DE10-Lite FPGA Development Board (2021-05-26, SystemVerilog, 16KB, 下载0次)
ARC4加解密实验室
ARC4 Encryption Decryption Lab (2018-05-22, SystemVerilog, 51198KB, 下载0次)
基于fpga的nand2俄罗斯方块
nand2tetris on an fpga (2016-08-28, SystemVerilog, 705KB, 下载0次)
Nexys 4板的单周期MIPS处理器，用System Verilog编写，带有俄罗斯方块演示程序
Single cycle MIPS processor for the Nexys 4 board written in System Verilog with a tetris demo program (2017-09-10, SystemVerilog, 4780KB, 下载0次)
硬件仿真采用Icarus Verilog EDA平台为半加器电路设计和测试平台。
Hardware Simulation using Icarus Verilog EDA Playground for a half adder circuit design and test bench. (2017-03-25, SystemVerilog, 1KB, 下载0次)
CARDIO超维计算的实现
A implemention of Hyperdimensional Computing for CARDIO (2021-04-28, SystemVerilog, 1476KB, 下载0次)
这是一个用Verilog语言编写的简单俄罗斯方块游戏项目，部署在BASYS3 FPGA开发板上，用于课程...
This is project of simple Tetris game written in Verilog langueage deployed on BASYS3 FPGA development board for course Digital electronic circuits 2 for Microelectronics in industry and medicine Field of Study on AGH University of Science and Technology in Krakow. Members: Monika Dutkowska, Micha? Kowalik. (2017-06-26, SystemVerilog, 765KB, 下载0次)
巴斯3乒乓球比赛
BASYS 3 - PONG GAME (2017-05-05, SystemVerilog, 86KB, 下载0次)